Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2001-01-26
2002-07-09
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S723000
Reexamination Certificate
active
06417532
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-020293, filed Jan. 28, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor module and more specifically to a package structure for a power semiconductor module for use in power conversion units, such as inverters, converters, etc., which require downsizing.
Power semiconductor modules in which power semiconductor devices, such as IGBTs, MOSFETs, bipolar transistors, etc., are mounted on the same circuit board are used in motor drive circuits by way of example.
FIG. 14
is an equivalent circuit diagram of a three-phase motor driving inverter using a power semiconductor module.
In this figure,
81
denotes power IGBT devices (chips),
82
a power supply terminal,
83
ground terminals,
84
input terminals, and
85
output terminals.
FIG. 15
is a schematic exterior view of a conventional power semiconductor module,
FIG. 16
is a plan view of the module of FIG.
15
. The module has a structure such that a plurality of power semiconductor devices (chips)
91
are mounted on a circuit board
92
and electrically connected by means of bonding wires to connectors in a case
94
to which pins
95
as module outer leads are attached.
In such a structure, the pins
95
are attached to the case
94
. This requires interconnect lines and bonding wires to be laid on the circuit board
92
to connect the semiconductor chips
91
and the pins
95
, which imposes restrictions on downsizing of the module.
Laying wirings on the circuit board
92
results in increased electrical resistance and inductance. Moreover, even if a request is made by an individual user for changing the circuit pattern on the circuit board
92
or the location of the pins
95
, it cannot be filled with ease because a significant design change is required.
Thus, the conventional power semiconductor module is subject to restrictions on downsizing due to the outer lead terminals
95
being attached to the case and suffers an increase in the electrical resistance and inductance due to the wirings.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power semiconductor module which can be reduced in size, can decrease the cost and the electrical resistance and inductance of wirings by reduction in size, and can flexibly fulfill individual user's requirements to change the circuit pattern on a circuit board and the location of outer lead terminals.
According to an aspect of the present invention, there is provided a power semiconductor module comprising: a circuit board having an insulating substrate and first and second interconnect patterns formed on the insulating substrate; a power semiconductor chip mounted on the first interconnect pattern; bonding wire for electrically connecting the semiconductor chip and the second interconnect pattern; outer lead terminals fixed to each of the first and second interconnect patterns; and a resin layer for covering at least the chip mounted surface of the circuit board in its entirety so that the tip of each of the outer lead terminals is exposed.
According to another aspect of the present invention, there is provided a power semiconductor module comprising: a circuit board having an insulating substrate and first and second interconnect patterns formed on the insulating substrate; a power semiconductor chip mounted on the first interconnect pattern; bonding wire for electrically connecting the semiconductor chip and the second interconnect pattern; outer lead terminals fixed to the first and second interconnect patterns; and a resin layer for covering at least each of the semiconductor chips mounted on the circuit board so that the tip of each of the outer lead terminals is exposed.
The present invention allows wirings between the semiconductor chips and the outer lead terminals to be shortened, reducing the electrical resistance and inductance of the wirings. The dimensions of the semiconductor module can be scaled down, reducing the cost. Individual user's requirements to change the circuit pattern on the circuit board and the location of the outer lead terminals can be fulfilled with flexibility.
In addition, when the insulation design for voltages for use with the semiconductor module permits, the resin layer is allowed to cover the chips only, which can lessen the effects of warp of the circuit board due to contraction of the resin layer.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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patent: 6297549 (2001-10-01), Hiyoshi
Imamura Kaoru
Nakao Satoshi
Tsunoda Tetsujiro
Umekawa Shinichi
Ho Hoai V.
Kabushiki Kaisha Toshiba
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