Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With switching speed enhancement means
Reexamination Certificate
2001-09-20
2003-08-12
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
With switching speed enhancement means
C257S133000, C257S139000, C257S140000, C257S146000, C257S147000, C257S155000, C257S490000, C257S495000, C257S341000, C257S610000, C257S611000, C257S612000
Reexamination Certificate
active
06605830
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a power semiconductor device for use in an inverter and a method of manufacturing the same.
2. Description of the Background Art
In recent years, motors have gone inverter-driven, for example, in the field of air conditioning in terms of energy saving, and an increasing number of power semiconductor devices for inverters have been produced.
There is an increasing need for such power semiconductor devices not only to reduce power dissipation but also to reduce size and costs in terms of space saving.
A background art power semiconductor device is described below with reference to
FIGS. 38 through 43
.
FIG. 38
is a circuit diagram of a three-phase inverter IV.
As illustrated in
FIG. 38
, the three-phase inverter IV comprises three inverters IV
1
to IV
3
. The inverter IV
1
includes IGBTs (insulated gate bipolar transistors, which are in some cases referred to simply as transistors hereinafter) Q
1
L and Q
1
U connected in series between a power supply line P providing a power supply voltage VDD and a power supply line N connected to a ground potential, and free wheeling diodes D
1
L and D
1
U connected in inverse-parallel with the transistors Q
1
L and Q
1
U, respectively. A connection node between the transistors Q
1
L and Q
1
U is connected to a first end of a load LU.
The inverter IV
2
is similar in construction to the inverter IV
1
. Specifically, the inverter IV
2
includes transistors Q
2
L and Q
2
U connected in series between the power supply lines P and N, and free wheeling diodes D
2
L and D
2
U connected in inverse-parallel with the transistors Q
2
L and Q
2
U, respectively. A connection node between the transistors Q
2
L and Q
2
U is connected to a first end of a load LW.
Likewise, the inverter IV
3
includes transistors Q
3
L and Q
3
U connected in series between the power supply lines P and N, and free wheeling diodes D
3
L and D
3
U connected in inverse-parallel with the transistors Q
3
L and Q
3
U, respectively. A connection node between the transistors Q
3
L and Q
3
U is connected to a first end of a load LV. The loads LU, LV and LW have respective second ends connected together.
In part of the inverter IV
1
shown in
FIG. 38
which is comprised of the transistor Q
1
L and the diode D
1
L, the reference characters E, C and G designate the emitter, collector and gate terminals of the transistor Q
1
L, respectively. The diode D
1
L has an anode terminal connected to the emitter terminal E and a cathode terminal connected to the collector terminal C.
A cross-sectional structure of the transistor Q
1
L and the diode D
1
L is described with reference to FIG.
39
. In the description below, it is assumed that the transistor Q
1
L is of an n-channel type and the diode D
1
L is a diode having a p-type anode formed on an n-type semiconductor substrate.
As illustrated in
FIG. 39
, the transistor Q
1
L includes a p-type base region
8
formed in an upper main surface of an n-type silicon substrate
1
T, and a plurality of trench-type gate electrodes
11
arranged in parallel and each extending through the p-type base region
8
in the direction of the depth thereof. A plurality of p-type semiconductor regions
12
containing a p-type impurity of a relatively high concentration are selectively formed in the surface of the p-type base region
8
in such a manner that each lies between adjacent two of the gate electrodes
11
. The p-type semiconductor regions
12
are provided for the purpose of making a satisfactory electric connection between the p-type base region
8
and emitter electrodes
19
.
A plurality of n-type emitter regions
9
containing an n-type impurity of a relatively high concentration are formed on the opposite sides of the respective p-type semiconductor regions
12
. The n-type emitter regions
9
are designed to contact respective gate insulation films (not shown) formed on the surface of the gate electrodes
11
. The silicon substrate
1
T serves herein as an n-type base layer of the IGBT.
The emitter electrodes
19
formed partially on the surface of the n-type emitter regions
9
are electrically connected to the emitter terminal E. The gate electrodes
11
are electrically connected to the gate terminal G. A plurality of parallel-connected IGBT structures constitute the transistor Q
1
L. A region in which the p-type base region
8
, the n-type emitter regions
9
and the gate electrodes
11
are formed is referred to hereinafter as a cell region
2
TC.
A plurality of p-type semiconductor regions
28
at a floating potential are arranged concentrically so as to surround the cell region
2
TC, to define an electric field relieving ring region
2
TG. The structure of the cell region
2
TC and the electric field relieving ring region
2
TG is generically referred to as an emitter-side structure
2
.
An n-type buffer layer
3
a
is formed on a lower main surface of the silicon substrate
1
T. A p-type collector layer
4
is formed on the surface of the n-type buffer layer
3
a
, and a collector electrode
5
a
of metal is formed on the surface of the p-type collector layer
4
.
FIG. 40
is a plan view of the transistor Q
1
L as viewed from above the emitter electrode. As illustrated in
FIG. 40
, the transistor Q
1
L is formed on a rectangular board, and is configured such that the rectangular electric field relieving ring region
2
TG surrounds the rectangular cell region
2
TC. An n-type semiconductor region
27
at a floating potential is formed to surround the electric field relieving ring region
2
TG.
In the cell region
2
TC, a plurality of gate lines GL are arranged in parallel, and are connected at their respective ends to a gate ring region GR defining the outer periphery of the cell region
2
TC. All of the gate lines GL are at a common potential. A gate pad GP is partially provided for electric connection between the gate lines GL and the exterior.
The spaces between the gate lines GL are covered with the emitter electrodes
19
, and an upper emitter electrode
190
for making electric connections between the emitter electrodes
19
covers the emitter electrodes
19
. For purposes of illustration, the upper emitter electrode
190
is shown with parts broken away in FIG.
40
.
The cross-section of the transistor Q
1
L shown in
FIG. 39
is a cross-section taken along the line A—A of FIG.
40
. The gate electrodes
11
shown in
FIG. 39
are only some of a plurality of gate electrodes
11
arranged longitudinally of the gate lines GL and each extending perpendicularly to the length of the gate lines GL.
Referring again to
FIG. 39
, the diode D
1
L includes a p-type anode layer
29
formed in an upper main surface of an n-type silicon substrate
1
D. A anode electrode not shown is formed on the surface of the anode layer
29
, and is electrically connected to the emitter terminal E. A region in which the anode layer
29
and the anode electrode are formed is referred to as an anode region
2
DA.
A plurality of p-type semiconductor regions
28
at a floating potential are arranged concentrically so as to surround the anode region
2
DA, to define an electric field relieving ring region
2
DG. The structure of the anode region
2
DA and the electric field relieving ring region
2
DG is generically referred to as an anode-side structure
2
D.
An n-type buffer layer
3
b
is formed on a lower main surface of the silicon substrate ID. An n-type semiconductor layer
6
containing an n-type impurity of a relatively high concentration is formed on the surface of the n-type buffer layer
3
b
, and a cathode electrode
5
b
of metal is formed on the surface of the n-type semiconductor layer
6
. The cathode electrode
5
b
is electrically connected to the collector terminal C.
The n-type semiconductor layer
6
is a layer for providing an ohmic contact between the cathode electrode
5
b
and the n-type buffer layer
3
b
. The silicon substrate ID i
Loke Steven
Mitsubishi Denki Kaisha
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