Power semiconductor device employing pin block connection arrang

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

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257678, 257687, 257691, 257177, 361728, 361823, H01L 2348, H01L 2352

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active

055192521

ABSTRACT:
In a power semiconductor device having a power circuit 1 and a control circuit 2 incorporated in a resin case 4, said circuits being mounted on different substrates 1a and 2a and interconnected internally, and power terminals 6 and control terminals 7 connected to the power and control circuits, respectively, being drawn out of the case, the power terminals 6, the control terminals 7 and lead pins 13 are preliminarily molded by an insert technique together with the case as the power terminals 6 and the control terminals 7 are arranged at the peripheral edge of the case 4 whereas the lead pins 13 for establishing interconnection between the power and control circuits are arranged on a pin block 12 provided at the middle stage within the case, and the substrate 1a for the power circuit is mounted on a heat dissipating metal base 11 combined with the bottom side of the case 4 and the substrate 2a for the control circuit on the pin block 12, with the power terminals, control terminals and the pin block being soldered together to assemble the power semiconductor device.

REFERENCES:
patent: 3444440 (1969-05-01), Bell et al.
patent: 3784725 (1974-01-01), Perkins et al.
patent: 4639759 (1987-01-01), Neidig et al.
patent: 4731644 (1988-03-01), Neidig
patent: 4884126 (1989-11-01), Harada et al.
patent: 4916502 (1990-04-01), Oshima
patent: 4920405 (1990-04-01), Inoh et al.
patent: 4965710 (1990-10-01), Pelly et al.
patent: 5172215 (1992-12-01), Kobayashi et al.
Japanese Abstract of JP 62-016554, published Jan. 24, 1987.
Japanese Abstract of JP 63-098140, published Apr. 28, 1988.

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