Power-scalable asynchronous architecture for a...

Details Power-scalable asynchronous architecture for a... Power-scalable asynchronous architecture for a...

2002-11-27

2004-06-01

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06744395

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to analog-to-digital converters (ADC), and more specifically to wave-pipelined ADCs.
BACKGROUND OF THE INVENTION
There are many analog-to-digital signal conversion (ADC) methods and apparatus. One of the well known ADC methods and apparatus is an synchronous pipeline ADC with error correction.
Reference is now made to
FIG. 1A
, a block diagram of prior art error correction synchronous pipeline ADC architecture
1
. Reference is made in parallel to
FIG. 1B
, a block diagram of a prior art sample stage
10
. ADC
1
may comprise a series of stages
10
. Each stage
10
may typically comprise one or more sub-stages, such as a sample/hold (SH) circuit
12
, ADC
14
, digital to analog converter (DAC)
16
, substractor
17
and amplifier
18
. As is commonly known in the art, the signal flow within and between stages
10
is regulated via synchronized strobes or clock signals. In
FIGS. 1A and 1B
, each progressive strobe or clock signal is represented by a “clk”, i.e. clk
1
, clk
2
, etc.
FIG. 1B
also illustrates an exemplary flow of a analog-to-digital conversion in exemplary stage
10
. An analog signal
22
is received by SH
12
, which samples and holds a sample analog value
24
. Upon clk
1
, SH
12
transfers sample
24
to ADC
14
and to substractor
17
. ADC
14
converts sample
24
to a digital signal
26
representative of the sample
24
. Upon clk
2
, ADC
14
transfers digital signal
26
to a register or latch (not shown) and to DAC
16
. DAC
16
receives digital signal
26
and converts it to a reconstructed analog signal
28
, representative of a quantization of sample
24
. Upon clk
3
, DAC
16
transmits reconstructed signal
28
to substractor
17
. Substractor
17
first calculates the quantization error between sample
24
and reconstructed signal
28
. Subtractor
17
then transmits the result to amplifier
18
. Upon clk
4
, amplifier
18
transmits multiplied signal
30
to the next stage
10
. Upon the next clk (not shown) the present cycle is repeated. Each stage
10
, and the elements comprised therein, progress synchronously with each other stage
10
.
It is noted that the above sample is a typical known in the art routine. As an example, ADC
14
is illustrated as 1.5 bit ADC, however, may be a single bit ADC or any other known in the art ADC. Stage
10
may have various alternative elements or may proceed upon alternative paths, however, the basic principle is similar to that presented in such that the entire process is regulated via synchronized clock strobes.
A disadvantage of the above procedure is that a comparator or stage may not complete its function during the clocked period, and may hence transmit a partial, incomplete or incorrect signal. Other drawbacks are the need for dedicated complex clocking circuits, the vulnerability to clock jitter and process variations, and a non-scalable power budget.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, there is now provided an apparatus and method of analog-to-digital conversion, wherein the elements and stages in an analog-to-digital (AD) wave pipeline architecture are not regulated via a synchronized clock. Rather, upon completion of each stage or function, the relevant element or stage transmits a “completed” signal, or an “ACK” signal to the next element/stage. The “ACK” signal then triggers that element/stage. Each stage thus receives the time necessary for proper operation, in a manner that is independent of the sampling frequency. Due to the novel “ACK” triggering method, the present invention is robust to technology scatter, process variations, and jitter problems. This robustness is in contrast to prior art circuits wherein each element and stage is allotted a predefined clocked period, which alternatively may be too much or too little time.
Another advantage of the present invention may be the elimination of global clocks in or between the stages. Inasmuch as no global clocks are needed, the design complexity may be reduced and the risk may be lowered.
In some preferred embodiment, each stage may be powered up only when it is required to process its input data. Furthermore, all stages may be powered down upon completion of the analog-to-digital converstion process. Thus, another advantage of the present invention may be scalable power consumption via application of a lower clock frequency, resulting in a reduced average power consumption.
In accordance with one aspect of the present invention, there is now provided a method for converting a signal from analog-to-digital domain. Upon receipt of an i
th
triggering signal, where 1≦i≦N, the method includes initiating at least a partial AD operation. Upon completion of the at least partial operation, the method may includes generating and transmitting an i
th
+1 triggering signal. The i
th
+1 triggering signal may be adapted to initiate an i
th
+1 at least partial operation, thereby creating an asynchronous process. The method further includes repeating the above operations until completion of the analog to digital conversion. In some embodiments of the present invention, upon completion of the conversion, i=N and the i
th
+1 operation is a power-down function.
In accordance with one aspect of the present invention, there is now provided ananalog-to-digital (AD) wave pipeline system. The system may include a plurality of AD pipeline stages in series, each of the stages, upon receipt of an i
th
triggering signal where 1≦i≦N, may intiate an AD operation. Upon completion of the operation, each stage may generate and transmit an i
th
+1th triggering signal adapted to initiate an i
th
+1 operation, thereby creating an asynchronous process.
In accordance with one aspect of the present invention, there is now provided an analog-to-digital (AD) stage. The stage may include a plurality of sub-stages, each sub-stage, upon receipt of an i
th
triggering signal where 1≦i≦N, may intiate a partial AD operation. Upon completion of the partial AD operation, each sub-stage may generate and transmit an i
th
+1 triggering signal adapted to initiate an i
th
+1 partial AD operation, thereby creating an asynchronous process. Each sub-stage may include a shut down mechanism adapted to shut down the sub-stage when i=N and upon receipt of the i
th
+1 triggering signal.


REFERENCES:
patent: 3599203 (1971-08-01), Conley
patent: 3968486 (1976-07-01), Gerdes
patent: 4275386 (1981-06-01), Michel et al.
patent: 4489309 (1984-12-01), Schlig
patent: 4544914 (1985-10-01), Chan et al.
patent: 4965579 (1990-10-01), Liu et al.
patent: 5043732 (1991-08-01), Robertson et al.
patent: 5107265 (1992-04-01), Sloane
patent: 5572212 (1996-11-01), Levinson et al.
patent: 5714955 (1998-02-01), Reay et al.
patent: 6124820 (2000-09-01), Norman et al.
patent: 6326914 (2001-12-01), Sevenhans
patent: 6340943 (2002-01-01), Chow et al.
Gilbert Promitzer, “12-Bit Low Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s”, IEEE Journal of Solid-State Circuits, vol. 36, No. 7, Jul. 2001, pp. 1138-1143.
D. G. Nairn et al, Algorithmic Analogue/Digital Convertor Based on Current Mirrors, Electronics Letters, Apr. 14, 1988, vol. 24, No. 8, pp. 471-472.
Gilbert Promitzer, 12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s, IEEE Journal of Solid-State Circuits, vol. 36, No. 7, Jul. 2001.

Affiliated with

Also associated with

Rating

Power-scalable asynchronous architecture for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power-scalable asynchronous architecture for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power-scalable asynchronous architecture for a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3314103