Power saving time slot interchanger with random read/write cycle

Details Power saving time slot interchanger with random read/write cycle Power saving time slot interchanger with random read/write cycle

1994-09-30

1996-04-16

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

370 66, 370 68, H04L 1252

Patent

active

055090052

ABSTRACT:
In a switching system of multiple time slot interchangers associated with outlet ports, each interchanger includes multiple data memories respectively connected to inlet ports and connected to the outlet port with which the interchanger is associated. A set of commands is established for each incoming data signal. The command set includes an inlet port number (IPN), an incoming slot number (ISN), an outlet port number (OPN), and an outgoing slot number (OSN). During a write cycle, one of the inlet ports is selected in accordance with the IPN command and one of the data memories which are associated with the selected inlet port is selected in accordance with the OPN command. The selected data memory is caused to store the data signal of an incoming time slot identified by the stored ISN command into one of its storage locations identified by the stored ISN command. During a subsequent read cycle, one of the outlet ports is selected in accordance with the OPN command and one of the data memories which are associated with the selected outlet port is selected in accordance with the stored IPN command. The selected data memory is caused to read a data signal from one of its storage locations identified by the ISN command onto an outgoing time slot identified by the OSN command.

REFERENCES:
patent: 4740953 (1988-04-01), Matsumoto et al.
patent: 5146455 (1992-08-01), Goke et al.
patent: 5351238 (1994-09-01), Ashi et al.

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