Power saving system for a memory controller

Details Power saving system for a memory controller Power saving system for a memory controller

1994-10-18

1995-12-05

Nelms, David C.

Static information storage and retrieval

Powering

Conservation of power

365226, 365236, G11C 700

Patent

active

054735726

ABSTRACT:
A memory controller is provided in which the address path is disabled by a sequencer to reduce power consumption when the sequencer is in an IDLE mode. When access is requested by the bus, the sequencer changes into an ALERT mode, thereby enabling the address path. Subsequently the sequencer then changes into an EXECUTE mode to perform data transfer operations. After the transfer is completed, the sequencer returns to the ALERT mode and an inactive time counter begins counting. If no access is requested before the counter reaches a predetermined number of counts, the sequencer returns to the IDLE mode and the address path is disabled to save power. However, if another cycle request occurs while in the ALERT mode, the EXECUTE mode is entered into immediately.

REFERENCES:
patent: 4381552 (1983-04-01), Nocilini et al.

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