Power saving scheme for a digital wireless communications termin

Details Power saving scheme for a digital wireless communications termin Power saving scheme for a digital wireless communications termin

1997-03-11

2000-02-22

Nguyen, Lee

Telecommunications

Receiver or analog modulated signal frequency converter

With particular receiver circuit

455 383, 455574, 370311, 375354, 327144, 327151, H04B 116

Patent

active

060290617

ABSTRACT:
According to the present invention, a mobile communications terminal includes a high accuracy clock for providing a timebase in a normal operating mode, a "slow clock" for providing the timebase in a low power mode of operation, and at least one processor coupled to the high accuracy clock and the "slow clock" for controlling the modes of operation. In a preferred embodiment, the mobile communications terminal includes a conversion signal processor (CSP), a digital signal processor (DSP), a communications protocol processor, and a radio frequency (RF) segment. The CSP, which includes a plurality of registers, interfaces with the DSP to execute the timing control functions for the terminal. In the normal operating mode, the timebase is maintained from the high accuracy clock. During inactive periods of terminal operation (e.g., in a paging mode), a sleep mode is enabled wherein the high accuracy clock source is disabled, the DSP, CSP, and communications protocol processor are shut down, and the "slow clock" provides the timebase for the terminal while a sleep counter is decremented for a given sleep interval. Upon expiration of the sleep interval or in response to an intervening external event (e.g., a keypad is depressed), a terminal wake-up is initiated so that the high accuracy clock resumes control of the timebase. Because the high accuracy clock and the "slow clock" are not synchronized, the CSP and DSP calibrate the "slow clock" to the high accuracy clock prior to the terminal entering the sleep mode.

REFERENCES:
patent: 5428820 (1995-06-01), Okada et al.
patent: 5737323 (1998-04-01), Lansdowne
patent: 5845204 (1998-12-01), Chapman et al.
A Microprocessor-Based Analog Wristwatch Chip with 3 Seconds/Year Accuracy, Didier Lanfranchi, Evert Dijkstra, Daniel Aebischer, Feb. 16, 1994.

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