Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2000-10-25
2001-09-18
Mai, Son (Department: 2818)
Static information storage and retrieval
Powering
Conservation of power
C365S226000
Reexamination Certificate
active
06292425
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of memory devices. More particularly, the invention relates to a method and arrangement for power saving on the fly during reading data from a memory device.
BACKGROUND OF THE INVENTION
The overall array architecture for a typical integrated circuit containing a memory includes a core memory, herein referred to as a core, and input/output circuitry, herein referred to as the periphery. The core generally contains a plurality of core cells (i.e. individual memory elements) that are arranged in an array of rows and columns. The core cells store at least one bit of data and are accessed through the periphery to external elements, such as a microprocessor, which require the data.
When the core is accessed, the microprocessor or other external element requests data stored in the core. Power is consumed both reading the data from the core to the periphery and driving the data onto the bus connecting the periphery and microprocessor. In general, there is a constant need to decrease the amount of power consumed while providing more powerful and faster elements and circuitry. Either decreasing the power used by individual components or minimizing the power used by the entire access process decreases the power used in retrieving sets of data from the core (either individual sets of bits, words or bytes, depending on the arrangement) and driving the sets of data along the bus to be read by a microprocessor or other external elements.
Thus, it is desirable to produce arrangements in which the power consumption is reduced. For example, large amounts of power are consumed when driving retrieved data along the bus dependent on the dynamical changes between successive sets of data being driven. This is to say that, power is consumed when data occupying a position on the bus (say data
0
occupying position
1
) and being driven along the bus during one clock cycle changes states (say data
1
occupying position
1
) and is driven along the bus during the next clock cycle. If the data occupying a particular position on the bus does not change from one clock cycle to the next clock cycle, significantly less power is consumed.
It is desirable to produce an arrangement in which the power consumption is reduced when driving successive sets of data to the bus, thereby increasing battery lifetime in portable computers, for example. In general, however, it is also desirable to increase the speed accessing data from the core, especially with the huge increase in the speed of microprocessors (and other external elements). Typically, the amount of time required to access data from the core is limited by the throughput of the accessing circuitry (usually limited by clocking the data through several subsections of the accessing circuitry). Thus, it is beneficial to produce an arrangement or method in which both the power consumption and throughput are decreased.
BRIEF SUMMARY OF THE INVENTION
In view of the above, an advantage of the present invention is to reduce the amount of power used in driving sets of data along the bus while maximizing the speed of data access, particularly during modes when data is “burst out” from the memory at high speed. An embodiment of the present invention is a method of power saving on the fly during reading of data from a memory device in which data presently selected from a core memory is selected synchronously with a clock pulse. The method includes determining whether majority of the presently introduced data has changed from previously introduced data from the core memory and delaying the presently introduced data. The delayed data is subjected to an exclusive-or logic function (XOR) with the majority determination and this data as well as the majority determination are driven separately to external elements requesting the present data. The data that has been subjected to the exclusive-or logic function is driven less than one clock pulse from the present selection of data from the core memory.
Another embodiment of the present invention is an arrangement of power saving on the fly during reading of data from a memory device in which a core memory containing selectable data is selected synchronously with a clock pulse. A determining mechanism determines whether the majority of data presently selected from the core cell has changed from previously selected data from the core memory. A delay mechanism delays the presently selected data and a plurality of first XOR gates subject the delayed data to an exclusive-or logic function with the majority determination. A plurality of drivers separately drive this data and the majority determination. The data that has been subjected to the exclusive-or logic function is driven less than one clock pulse from the selection of the present data from the core memory. In this manner power is saved, as the state of the majority of the data being driven from one data set to the next remains unchanged, and output speed is increased as the data, once clocked into the arrangement, is driven in less than a clock pulse.
The following figures and detailed description of the preferred embodiments will more clearly demonstrate these and other objects and advantages of the invention.
REFERENCES:
patent: 5712826 (1998-01-01), Wong et al.
patent: 5761144 (1998-06-01), Fukuzumi
patent: 6067627 (2000-05-01), Reents
patent: 6073223 (2000-06-01), McAllister et al.
Al-Shamma Ali K.
Cleveland Lee E.
Advanced Micro Devices , Inc.
Mai Son
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