Power saving method for performing additions and...

Details Power saving method for performing additions and... Power saving method for performing additions and...

1999-11-09

2002-11-12

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C711S220000

Reexamination Certificate

active

06480874

ABSTRACT:

FIELD OF THE INVENTION
Power saving method for performing additions and subtractions and device thereof and especially a power saving address generation unit and a method thereof.
BACKGROUND OF THE INVENTION
Multi-bit adders, and especially high-speed adders are comprised of many transistors. For example, a 32 bit adder is comprised of more than a thousand CMOS transistors. 32-bit adders and even larger adders are extensively used in modern processor address generating units.
A premium is placed upon low power consumption of modern processors, especially in electrical devices that are powered by batteries. It is very important to reduce the energy consumption associated with very frequent operations such as subtraction and additions. It is convenient to reduce the power associated with address generation, especially when the subtraction and addition involve an operand (“old” address) and a constant K, wherein K usually equals 2
n
.
There is a need of a power saving method for performing additions and subtractions and device thereof and especially a power saving address generation unit and a method thereof.


REFERENCES:
patent: 5260898 (1993-11-01), Richardson
patent: 5333119 (1994-07-01), Raatz et al.
patent: 5828591 (1998-10-01), Rotstain
patent: 6298369 (2001-10-01), Nguyen

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