Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2002-04-02
2004-03-30
Patel, Rajnikant B. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C307S066000
Reexamination Certificate
active
06713994
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power saving integrated circuit having a power saving function and a method of controlling the same, and more particularly to a reduction in power consumption of the integrated circuit
The present application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2001-113907, filed Apr. 12, 2001, which is herein incorporated by reference in its entirely for all purposes.
2. Description of the Related Art
A conventional integrated circuit is constructed with a plurality of circuit blocks having various uses, each of which includes at least one circuit element, respectively Generally, the conventional integrated circuit includes a power supply circuit which supplies stable power, a switching circuit which switches a supply of a power supply voltage “ON” and “OFF”, a power control circuit which controls a switching of the switching circuit, and an operating circuit which receives the power supply voltage through the switching circuit and executes various operating functions.
Recently, a power saving mode function, which shuts off the supply of the power supply voltage to an unused circuit block, is provided in the power control circuit to reduce power consumption, in consideration of the environment and a request for the power saving. On the other hand, detection and notification functions of the power saving mode, which detect the unused circuit block and inform the power control circuit, are provided in the operating circuit.
FIG. 5
is a block diagram of a conventional integrated circuit
200
having the power saving mode. The integrated circuit
200
includes a power supply
210
which supplies a power supply voltage Vd, an operating circuit
1
which executes various operating functions, a power control circuit
2
having a power saving mode function, and a transistor
30
as a switching circuit. The power supply voltage Vd is supplied to the power control circuit
2
and the switching circuit
30
. A power supply voltage Vda is supplied to the operating circuit
1
through the switching circuit
30
.
The operating circuit
1
may include, for example, a CPU (Central Processing Unit)
11
. The CPU
11
detects a power saving mode of the operating circuit
1
by receiving a first signal which shows a transition from a normal active mode to the power saving mode, and outputs a notification signal PS to the power control circuit
2
. The notification signal PS indicates that the supply of the power supply voltage Vd to the unused operating circuit
1
should be shut off.
The power control circuit
2
includes a controller
21
, a counter
22
and an OR gate
23
. The controller
21
shuts off the supply of a clock signal CL to the operating circuit
1
, and then outputs a power control signal PC to the transistor
30
and also starts to output a reset signal RS to the operating circuit
1
, in response to the notification signal PS. The transistor
30
shuts off the supply of the power supply voltage Vda in response to the power control signal PC. On the other hand, the controller
2
resumes the supply of the clock signal CL to the operating circuit
1
, and stops outputting the power control signal PC to the transistor
30
, in response to a release signal WU which indicates release of an interruption of the supply of the power supply voltage Vda. And, the controller
21
continues to output the reset signal RS during a reset delay period which is set in the counter
22
.
The counter
22
counts the reset delay period and outputs the reset signal RS to the operating circuit
1
during the reset delay period when the power control circuit
2
releases the interruption of the supply of the power supply voltage Vda. The OR gate
23
controls a switching of the clock signal CL.
The integrated circuit
200
can initialize the operating circuit
1
due to input the reset signal RS into the operating circuit
1
. Moreover, the integrated circuit
200
can inhibit a malfunction of the operating circuit
1
which results from a transient voltage of a rising period of the power supply
210
, by continuing to output of the reset signal RS until the power supply
210
recovers to an active level and the power supply voltage Vda level settles.
FIGS.
6
(
a
) thorough
6
(
e
) are timing charts showing timing various signals in the conventional power saving integrated circuit
200
. FIG.
6
(
a
) is a waveform of the power supply voltage Vda which is supplied to the operating circuit
1
through the transistor
30
. FIG.
6
(
b
) is a signal waveform of the clock signal CL which is output from the OR gate
23
. FIG.
6
(
c
) is a signal waveform of the reset signal RS which is output from the counter
22
. FIG.
6
(
d
) is a signal waveform of the power control signal PC. FIG.
6
(
e
) is a signal waveform of the release signal WU.
During a period TM
1
, when the CPU
11
detects the power saving mode, the CPU
11
outputs the notification signal PS to the controller
21
. At this point, the controller
21
outputs a gate control signal GC to the OR gate
23
to stop the clock signal CL at a time t
1
. As a result, a period TM
2
begins, which indicates a preparation period for shutting off the supply of the power supply voltage Vda to the operating circuit
1
.
At a time t
2
, which indicates a termination of the period TM
2
, the controller
21
outputs the power control signal PC to the transistor
30
to shut off the supply of the power supply voltage Vda for the operating circuit
1
. At the same time, the controller
21
starts to output the reset signal RS to the operating circuit
1
through the counter
22
. As a result, a period TM
3
begins, which indicates a period for shutting off the supply of the power supply voltage Vda to the operating circuit
1
. After the start of the period TM
3
, the power supply voltage Vda level gradually falls due to an interruption of the supply of the power supply voltage Vda.
At a time t
3
, the controller
21
suspends the output of the power control signal PC to release the interruption of the supply of the power supply voltage Vda in accordance with the release signal WU, and outputs the gate control signal GC to the OR gate
23
. At this time, the controller
21
sets a reset delay period Tw
1
into the counter
22
so as to continue the output of the reset signal RS for the period Tw
1
. The counter
22
starts to count the reset delay period Tw
1
. As a result, a period TM
4
begins, which indicates a recovery period until the termination of the reset signal RS.
During the period TM
4
, the power supply voltage Vda level gradually rises to the rated voltage level, and settles at a time t
4
. A rise time tv
1
of the power supply voltage Vda fluctuates due to variable factors, for example the power voltage level of the integrated circuit
200
and the frequency of the clock signal CL. When the power voltage level of the integrated circuit
200
is greater, the integrated circuit
200
needs a longer the rise time tv
1
. And, when the frequency of the clock signal CL is greater, the integrated circuit also needs a longer rise time tv
1
. The rise time tv
1
is set in accordance with the sum of an effective rise time ts
1
and a fluctuation margin tm
1
due to the variable factors. A reset period tr
1
shows a period to reset the counter
22
after the power supply voltage Vda has settled.
The counter
22
is set such that a reset delay period tw
1
is equal to the sum of rise time tv
1
and the reset period tr
1
. The counter
22
continues to output the reset signal RS until a termination of the reset delay period tw
1
, and stops outputting the reset signal RS at a time t
6
which indicates the termination of the reset delay period tw
1
. As a result, the operating circuit
1
recovers from the power saving mode to the normal active mode. A period TM
5
indicates the recovered normal active mode of the implementing circuit
1
starts.
However, in the conventional power saving integrated circuit, it is necessary to set a relatively lon
Oki Electric Industry Co. Ltd.
Patel Rajnikant B.
Volentine & Francos, PLLC
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