Power saving feature for components having built-in testing logi

Excavating

Patent

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Details

3241581, 395425, 395750, H04B 1700, G01R 3102, G06F 130

Patent

active

053772008

ABSTRACT:
A configuration register enables built-in testing logic during testing operations, and disables the testing logic during non-testing operations. When enabled, the testing logic is in a normal state, and when disabled the testing logic is in a low power state. The configuration register generates a control signal to the testing logic, the control signal being is responsive to signals received at a key input and a reset input of the configuration register. When the reset input of the configuration register is triggered, the control signal drives the testing logic to the low power state. When a signal matching a predetermined data pattern is applied to the key input, the control signal drives the testing logic to the normal state.

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