Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2001-02-07
2004-05-25
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S051000, C345S053000, C345S068000, C345S094000, C345S208000, C345S210000, C345S214000, C345S215000
Reexamination Certificate
active
06741238
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving circuit for a display panel, and in particular, to a power saving circuit for a liquid crystal display (LCD) panel and a plasma display panel (PDP).
2. Background of the Related Art
FIG. 1
is a cross-sectional view illustrating a pixel structure of a plasma display panel (PDP) according to the related art. As shown in
FIG. 1
, one pixel includes an upper plate
6
and a lower plate
7
that are aligned to face each other separated by a discharge space
8
. In
FIG. 1
, the upper plate
6
forms a display screen panel, and the discharge space
8
is sealed up with a discharge excitation gas such as Ne—Xe mixture gas or He—Xe mixture gas. A scan electrode
1
and a sustain electrode
2
are positioned on the upper plate, facing each other, and a data electrode
3
(or address electrode) aligned orthogonal to the scan electrode
1
and the sustain electrode
2
is formed on the lower plate
7
. A dielectric body (not shown) is spread on the data electrode
3
. In addition, a barrier rib
4
for dividing each pixel is arranged on the data electrode, and a phosphor layer
5
is spread on the dielectric body covering the barrier rib
4
and the address electrode
3
.
Accordingly, three grooves corresponding to red (R), green (G) and blue (B) and spread along the barrier rib
4
compose one pixel. The plasma gas reacts with the phosphor layer
5
, and thus, the pixel generates lights of red, green and blue.
FIG. 3
illustrates a related art PDP driving circuit. As shown in
FIG. 3
, the related art PDP driving circuit includes a PDP
9
, a scan drive IC
10
, a data drive IC
11
, a scan common pulse generator
12
, a sustain pulse generator
13
, a scan common energy recovering unit
14
and a sustain energy recovering unit
15
.
Each pixel of the PDP
9
is operated and controlled by a voltage inputted to the scan electrode
1
, the sustain electrode
2
and the data electrode
3
. The pixels positioned on a line 1-480 selected by the scan electrode
1
receive an effective data through the data electrode
3
. The data inputted through the data electrode
3
causes discharge to the scan electrode
1
and the sustain electrode
2
. Selection of one line implies that the voltage is applied to the scan electrode
1
. Such an operation is performed by the scan drive IC
10
, the scan common pulse generator
12
and a common voltage generator (not shown).
The scan common pulse generator
12
outputs a common pulse signal of VH level (VH>VDD) according to control signals {circle around (
3
)}, {circle around (
4
)} and the scan drive IC
10
outputs a pulse signal of VDD level according to a control signal {circle around (
2
)}. Accordingly, an added value of the common pulse signal and the pulse signal, namely a scan pulse signal is inputted to the scan electrode
1
, thereby selecting one scan electrode line.
When one scan electrode line is selected, the data drive IC
11
outputs the effective data (video data) to the pixels existing on the corresponding display line. That is, the data drive IC
11
applies the data pulse of VDD level to the address electrode
3
according to a pixel data {circle around (
1
)} provided by a memory (not shown), thereby writing the pixel data on the pixels of the selected line.
The above operation is sequentially performed during an address period of FIG.
4
. When the write operation of the pixel data is finished in regard to the pixels on all of the scan lines 1-480, the respective pixels emit a light during a sustain period as shown in FIG.
4
. In the sustain period, the scan common pulse generator
12
outputs a first discharge sustain pulse signal of VH level according to the control signals {circle around (
3
)}, {circle around (
4
)}, and the sustain pulse generator
13
outputs a second discharge sustain pulse signal of VH level according to control signals {circle around (
5
)}, {circle around (
6
)}, at a timing different relative to a timing of the first discharge sustain pulse signal.
Accordingly, during the sustain period, the first and second discharge sustain pulse signals are alternately applied to the scan electrode
1
and the sustain electrode
2
. Thus, the PDP generates a light recognizable by human beings. Numbers of the first and second discharge sustain pulse signals applied to the scan electrode
1
and the sustain electrode
2
are discriminated for a gradation display as described below.
As described above, when the operation for one sub-frame is finished by sequentially carrying out the address period and the sustain period, the recorded data of the pixels must be all deleted for a next sub-frame. This period is a reset period as shown in FIG.
4
.
Thus, in the PDP, the gradation is embodied in a digital method, which differs from a general cathode ray tube (CRT). That is, the CRT controls a degree of luminance by varying a strength of an electron beam injected to the respective pixels in an analog method, while the PDP controls the degree of luminance of the phosphor layer
5
by discriminating the numbers of the first and second discharge sustain pulse signals.
As shown in
FIG. 2
, to embody 256 gradation for a display, one field (16.7 ms), which is a time for outputting one frame on a display screen according to the NTSC standard, is divided into 8 sub-frames SF
1
~SF
8
. The above-described operation of the reset period, scan period and sustain period is performed on each sub-frame. As shown in
FIG. 2
, the sustain period is increased in the respective frames at a ratio of 2
n
(n=0, 7). In addition, a luminance number of each sub-frame is discriminated into 8 bits. For instance, in order to set the luminance of a specific pixel to be 112 level, the addressing is performed on the 4th, 5th and 6th sub-frames (2
4
+2
5
+2
6
=112). So as to maximize the luminance, the addressing is carried out on the whole frame.
Accordingly, to drive the related art PDP, the scan pulse signal is first applied to the scan electrode
1
, and the data pulse signal is applied to the data electrode
3
with an identical timing to perform the record discharge. Then, the discharge sustain pulse signal is alternately applied to the scan electrode
1
and the sustain electrode
2
to perform the sustain discharge to sustain the luminance.
As shown in
FIGS. 3-4
, the sustain discharge is performed by charging or discharging a capacitance unit (not shown) between the panel electrodes. It is conventionally known that most of the pixel luminance results from the sustain discharge. As a result, the consumption power of the PDP is considerably dependent upon the consumption power of the sustain period. When a large-sized panel is driven, the consumption power of the entire PDP is increased because of the increase of the capacitance and the driving power between the panel electrodes. Therefore, various methods have been suggested for reducing power consumption during the sustain discharge, such as recovering an ineffective power lost by the discharge during the sustain period and recycling it during the charge.
As shown in
FIG. 3
, the related art operation for recovering and recycling the power consumed during the sustain period is performed by the scan common energy recovering unit
14
and the sustain energy recovering unit
15
. The scan common energy recovering unit
14
is connected to an output node of the scan common pulse generator
12
, and the sustain energy recovering unit
15
is connected to an output node of the sustain pulse generator
13
. The constitution and operation of the scan common energy recovering unit
14
and the sustain energy recovering unit
15
are identical. The operation of the scan common energy recovering unit
14
will now be described.
FIGS. 5A and 5B
respectively illustrate paths of the scan common energy recovering unit
14
for recovering and recycling the scan common pulse P
SC
outputted from the scan common pulse generator
12
during the sustain period.
FIG. 6
illustrates waveform
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Shankar Vijay
Shapiro Leonid
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