Power saving arrangement for a clocked digital circuit

Details Power saving arrangement for a clocked digital circuit Power saving arrangement for a clocked digital circuit

1990-06-01

1991-06-18

Lall, Parshotam S.

Boots, shoes, and leggings

364200, 3642731, 365227, G06F 104, H03K 504

Patent

active

050253875

ABSTRACT:
A power saving arrangement for a microcomputer having a first clock signal operating at a predetermined frequency employs a reduced clock frequency to peripheral circuitry to limit power consumption during a disable or halt mode. A control circuit disables a clock signal provided to the microcomputer, while a clock divider divides the predetermined frequency to generate a reduced frequency signal upon which the peripheral circuitry may operate. After receiving an external wake-up signal, the peripheral circuitry interrupts the microcomputer in order to revert the microcomputer back to normal operation.

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Zilog, Advance Product Specification, Z84C80 GLU, General Logic Unit, Oct. 1986.
"CMOS 280 Clock Generator/Controller", Toshiba Integrated Circuit Technical Data, No. TMPZ84C60P, pp. 273-289.

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