Power reset circuit of a flash memory device

Details Power reset circuit of a flash memory device Power reset circuit of a flash memory device

1999-12-22

2001-02-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S226000, C365S189090

Reexamination Certificate

active

06185129

ABSTRACT:

FIELD OF THE INVENTION
1. Field of the Invention
The present invention relates to a power reset circuit of a flash memory device. In particular, the present invention relates to a power reset circuit of a flash memory device which can feed back the output of the power reset circuit to remove a standby current, thus improving the integration degree of a device.
2. Description of the Prior Art
Upon an initial operation of the flash memory device, respective components of the device has to maintain an initial set value so that they can perform a normal operation. Therefore, in the operation of the flash memory device, it is important to initiate (or reset) the device.
The power reset circuit performs the finction of initializing the device. Generally, the standby current of the flash memory device is limited within about 5 &mgr;A. Therefore, upon power-up, after the devices are initialized, the power reset circuit does not have to consume any current.
A conventional power reset circuit will be explained by reference to FIG.
1
.
FIG. 1
is a circuit diagram for illustrating a conventional power reset circuit.
A delay section
11
for delaying the increase of the supply voltage is connected between the supply terminal Vcc and the first node K
1
, and a fourteenth NMOS transistor N
14
the gate of which is connected to the first node K
1
is connected between the first node K
1
and tie supply terminal Vcc.
In the delay section
11
, a plurality of PMOS transistors P
101
to P
112
the gates of which are connected to the ground terminal Vss, respectively, are serially connected between the supply terminal Vcc and the second node K
2
, and a plurality of PMOS transistors P
113
to P
132
the gates of which are connected to the ground terminal Vss, respectively, are serially connected between the second node K
2
and the third node K
3
. Also, a first capacitor C
1
consisted of NMOS transistors is connected between the third node K
3
and the ground terminal Vss. A resistor R is connected between the fourteenth NMOS transistor N
14
and the fourth node K
4
and a fifteenth transistor N
15
the gate of which is connected to the fourth node K
4
, is connected between the fourth node K
4
and the supply terminal Vcc.
Further first and second inverters
12
and
13
are connected between the supply terminal Vcc and the ground terminal Vss, respectively. In the first inverter
12
, a first PMOS transistor P
1
the gate of which is connected to the fourth node K
4
, a PMOS transistor P
2
and a third PMOS transistor P
3
the gate of which is connected to the ground terminal Vss are serially connected between the supply terminal Vcc and the fifth node K
5
. Also, the first to fifth NMOS transistors N
1
to N
5
the gates of which are connected to the supply terminal Vcc are serially connected between the fifth node K
5
and the ground terminal Vss.
In the second inverter
13
, a fourth PMOS transistor P
4
the gate of which is connected to the fourth node K
4
a fifth PMOS transistor PS the gate of which is connected to the ground terminal Vss are serially connected between the supply terminal Vcc and the sixth node K
6
. Seventh to ninth NMOS transistors N
7
to N
9
the gates of which are connected to the fifth node K
5
are connected between the sixth node K
6
and the ground terminal Vss.
Also, the sixth NMOS transistor N
6
the gate of which is connected to the fifth node KS is connected the supply terminal Vcc and the fifth node K
5
, and a second capacitor C
2
consisted of the NMOS transistors is connected between the fifth node K
5
and the ground terminal Vss. The first to sixth inverters I
1
to I
6
are serially connected between the sixth node and the output terminal PURST, and a third capacitor C
3
consisted of the PMOS transistors is connected between the supply terminal Vcc and the sixth node K
6
. Also, tenth to thirteenth NMOS transistors N
10
to N
13
the gates of which are connected to the fourth node K
4
, respectively, are serially connected between the sixth node K
6
and the ground terminal Vss. NMOS transistors N
7
to N
9
gates of which are connected to the fifth node K
5
are connected between the ground terminal and the sixth node K
6
.
The operation of the power reset circuit constructed as above may be explained by dividing three steps as the supply voltage thereof increases from 0V to Vcc slowly.
First, the initial state in which the supply voltage is applied will be explained.
At initial state, the voltage level of the fourth node K
4
being an input terminal of the first inverter I
1
is maintained at low level. Thereby, the first PMOS transistor P
1
is turned on and the supply voltage is applied to the fifth node K
5
via the second and third PMOS transistors P
2
and P
3
. At this time, as a low voltage level of the initial state is applied to the gates of the first to fifth NMOS transistors N
1
to N
5
, the first to fifth NMOS transistors N
1
to N
5
are kept turned off. At the same time, the fourth PMOS transistor P
4
will be turned on by the voltage level of the fourth node K
4
being an input terminal of the second inverter I
2
, and thereby the supply voltage is applied to the sixth node K
6
via the fifth PMOS transistor P
5
. Then, as the voltage level of the sixth node K
6
is higher than that of the fifth node K
5
, the seventh to ninth NMOS transistors N
7
to N
9
are kept turned off Also, as the voltage level of the supply voltage is at low level, the sixth node K
6
is kept at a low level. Accordingly, a low level of voltage is outputted via the output terminal PURST.
Second, the case that the supply voltage is maintained more than a constant level will be explained.
In this case, as the supply voltage is not so higher enough to turn on the NMOS transistor, a constant increased supply voltage is applied to the fifth node K
5
, Also, a constant increased supply voltage is applied to the sixth node K
6
. However, as the voltage level of the sixth node K
6
is higher than that of the fifth node K
5
, a high level of voltage is outputted by the second bootstrap circuit
29
via the output terminal PURST and the initial operation for the device is accomplished.
Third, the state in which the supply voltage is completely increased will be explained.
After the supply voltage becomes a constant level to accomplish the initial operation, when a high level of voltage is outputted via the first node K
1
being the output terminal of the delay section
11
, the first and fourth PMOS transistors P
1
P
4
will be turned off and the tenth to thirteenth AMOS transistors N
10
to N
13
will be turned on, thus making the sixth node K
6
a low level. Therefore, the operation of the first and second inverters I
1
and I
2
will stop and a low level of voltage will be outputted via tle output terminal PURST, thus stopping the initial operation.
The fourteenth and fifteenth NMOS transistors N
14
and N
15
are consisted of transistors having a low threshold voltage, i. e, about 0.3V than a different transistor. In this case, if the supply voltage is lowered to 0V, it functions to lower the voltage level of the fourth node K
4
to 0V.
However, in the conventional power reset circuit, as the delay section
11
for delaying the increase of the supply voltage upon power-up is consisted of a plurality of PMOS transistors P
101
to P
132
and a capacitor C
1
, the area in which the power reset circuit occupies in the flash memory device is large. Also, if the power-up time is too long, the delay section
11
does not operate corresponding to the long power-up time.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the problems involved in the prior art, and to provide a power reset circuit of a flash memory device which can feed back the output value of the power reset circuit to remove a standby current, thus improving the integration degree of a device.
In order to accomplish the above object, the power reset circuit of the flash memory device according to the present invention is characterized in that it comprises a first bootstrap ci

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