Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-08-27
2002-09-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06455336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a power reduction method and design technique for the burn-in of chips and electrical devices, and more particularly pertains to a design and burn-in technique that effectively reduces power consumption during burn-in for devices that have high power consumption at stress conditions.
2. Discussion of the Prior Art
Burn-in provides a means of accelerating reliability testing of defects in chips that are activated by high temperatures and/or voltages by raising the temperature and voltage of the chips for some duration of time to conditions that will significantly accelerate those defects (i.e. IBM typically requires burn-in at 140Ì{haeck over (S)}C, at 1.5×Vusage). Factors such as technology advancement in submicron processing, device design and increasingly complex device designs incorporating millions of transistors have made burn-in of chips much more difficult because of factors such as substantially higher instantaneous current and subthreshold leakage which contribute to high currents at burn-in conditions. As the size of devices continues to shrink and designs incorporate more transistors, many large scale chip designs can no longer be burned-in using standard manufacturing burn-in tools. Very expensive and low capacity high-power burn-in tools are becoming more essential as changes in technology drive the need for this capability. Some present techniques for extending the life of standard manufacturing burn-in tools include:
(1) Depopulate the burn-in oven to provide better heat dissipation characteristics in the oven. Drawback: Lower throughput (less parts burned-in per stress).
(2) Reduced burn-in conditions (i.e. lower temperatures and voltages)._ Drawback: Burn-in duration exponentially increases in order to satisfy-reliability_targets.
(3) Screen parts prior to burn-in in order to weed out high power parts.Drawback: The extensive resources required to perform correlation and maintain in a manufacturing environment. Process variations over time may require further analysis to reevaluate the screening process. This also poses a problem with respect to high power parts that are screened out and must be tested in some other manner.
(4) Individual Chip Temperature Control (ICTC) where each chip is heated individually to stress conditions.Drawback: Extends today's toolset capability from 3 watts/part maximum to about 10 watts/part.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a power reduction method and design technique for burn-in.
A further object of the subject invention is the provision of a design and burn-in technique that effectively reduces power consumption during burn-in for devices that have shrinking voltages, high instantaneous current, subthreshold leakage, high currents at stress conditions and high thermal dissipation.
The present invention provides a power reduction method and design technique for burn-in that is easily implemented into current ASIC and microprocessor design techniques, and that reduces chip power consumption during burn-in. More specifically, the power reduction method and design technique is compatible with LSSD (Level Sensitive Scan Design) scan architecture which is used in ASIC libraries and microprocessor designs, and can be used to exercise parts during burn-in.
The present invention segments the chip design into different segments, each segment having a corresponding power supply segment. Each chip section is tested at elevated stress conditions one section at a time by powering on only the power supply segment that corresponds to the chip section under test. All other power supply segments are powered off, thereby reducing power consumption during burn-in. This process is repeated for each chip segment until all segments are burned-in.
The segmenting of the power supply can be implemented by several methods. Three methods are discussed herein: 1. Completely separate power plane segments or grids;2. Isolated power plane segments or grids during burn-in;3. Isolated power plane segments or grids for MTCMOS used during burn-in.
REFERENCES:
patent: 4527254 (1985-07-01), Ryan et al.
patent: 4711024 (1987-12-01), Russell
patent: 5315598 (1994-05-01), Tran
patent: 5636171 (1997-06-01), Yoo et al.
patent: 5654930 (1997-08-01), Yoo et al.
patent: 5926423 (1999-07-01), Jeong
patent: 5930269 (1999-07-01), Tsukamoto et al.
patent: 5956279 (1999-09-01), Mo et al.
patent: 6026038 (2000-02-01), Cho et al.
patent: 6125465 (2000-09-01), McNamara
Berndlmaier Zachary E.
Bilak Mark R.
Rohrer Norman J.
Niebling John F.
Scully Scott Murphy & Presser
Stevenson André C
Walsh Robert A.
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