Power reduction in a data processing system using pipeline regis

Details Power reduction in a data processing system using pipeline regis Power reduction in a data processing system using pipeline regis

1994-12-22

1997-09-09

Mai, Tan V.

Boots, shoes, and leggings

364707, G06F 738, G06F 100

Patent

active

056663005

ABSTRACT:
In a data arithmetic logic unit (54), power consumption is reduced by eliminating unnecessary write backs to the destination register (82) following a MAC (multiply/accumulate) operation. A series of instructions provided to the data ALU (arithmetic/logic) (54) are monitored by a control circuit (89). When two or more consecutive instructions having identical destinations for a result are detected, the result is written to a pipeline register (78) instead of to the destination register (82) named in the consecutive instructions. Thus, only a short, lightly loaded bus to the pipeline register (78) is driven, instead of the longer heavily loaded bus to the destination register (82).

REFERENCES:
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4843585 (1989-06-01), Williams
patent: 5204828 (1993-04-01), Kohn
Motorola Inc., "DSP56000 Digital Signal Processor Family Manual", 1992, pp. 3-1 through 3-19.

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