Power reduction for delay locked loop circuits

Details Power reduction for delay locked loop circuits Power reduction for delay locked loop circuits

2002-08-29

2004-05-18

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S236000, C327S161000

Reexamination Certificate

active

06737897

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and in particular to delay lines in integrated circuits.
BACKGROUND OF THE INVENTION
Digital delay lines are parts of delay locked loops, which are often used in integrated circuits (IC) to generate an internal clock signal from an external clock signal. The internal clock signal is a delayed version of the external clock signal. The internal clock signal usually has the same frequency as the external clock signal. Although they have the same frequency, the internal clock signal is preferable because it can be adapted to control internal functions of the IC easier than the external clock signal. The internal clock signal is more accurate, and matches the operating condition of the IC better than the external clock signal.
A typical digital delay line has a number of delay cells connected in series. The last delay cell in the series connects to an output node. All delay cells connect to a common input node, which receives an external clock signal. A delay cell delays the clock signal by a certain amount of delay. The internal clock signal is generated after the external clock signal is delayed by some or all of the delay cells.
Although the external clock signal is present at the inputs of all the delay cells of the delay line, the external clock signal is allowed to enter the delay line at only one entry point at one of the delay cells. The entry point of the external clock signal is usually selected by a shift register. After the external clock signal enters the delay line, it propagates from the entry point downstream to the last delay cell and to the output node of the delay line.
In a series-connected delay cells, “downstream” refers to the portion of the delay line from the entry point toward the last delay cell located at one end of the series, whereas “upstream” refers to the portion of delay line from the entry point toward the first delay cell located at the other end of the series. In a typical digital delay line, the delay cells downstream propagate the clock signal from the entry point to the output node. Thus, only the downstream delay cells apply delay to the external clock signal. The upstream delay cells are not used to propagate the external clock signal.
Although the upstream delay cells are not used, they are affected by the external clock signal. Since the external clock signal is present at the inputs of all delay cells, both downstream and upstream delay cells, the external clock signal affects the upstream delay cells by causing their internal logic gates to toggle. Since the upstream delay cells are not used, the toggling of the upstream delay cells is unnecessary. The toggling creates noise and also dissipates power unnecessarily.
Reducing the noise or power dissipation of a digital delay line would be advantageous; reducing both would be even better.
SUMMARY OF THE INVENTION
The present invention is a novel digital delay circuit having reduced noise and power dissipation.
In one aspect, the delay circuit includes an input node to receive a clock signal, an output node, and a plurality of propagation gates connected in series with one of the propagation gates connected to the output node. The delay circuit also includes a plurality of entry-point gates connected to the input node and the propagation gates. Moreover, the delay circuit includes a plurality of register cells connected to the propagation gates and the entry-point gates. The register cells select one of the entry-point gates to be an active entry-point gate to allow the clock signal to enter the active entry-point gate and propagate to the output node, such that propagation gates and entry-point gates preceding the active entry-gate are not toggling.
In another aspect, a method of reducing noise and power dissipation of a delay circuit is provided. The method includes receiving a clock signal at an input node. Next, an entry point at a delay cell among a plurality of delay cells connected in series is selected. Subsequently, from the entry point, the clock signal propagates to an output node such that internal gates of delay cells preceding the entry point are not toggling.


REFERENCES:
patent: 6069506 (2000-05-01), Miller, Jr. et al.
patent: 6100736 (2000-08-01), Wu et al.
patent: 6445231 (2002-09-01), Baker et al.
patent: 6448756 (2002-09-01), Loughmiller

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