Power rails glitch noise insensitive charge pump

Details Power rails glitch noise insensitive charge pump Power rails glitch noise insensitive charge pump

2001-12-20

2004-08-10

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S008000, C327S148000

Reexamination Certificate

active

06774730

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the field of mixed signal integrated circuits (IC) utilizing phase-locked loop (PLL) circuits, and more particularly to a power rails glitch noise insensitive PLL charge pump suitable for use in such PLL circuits that is capable of substantially diminishing the adverse effects of supply/ground glitches upon the capability of the PLL circuits to stay in lock.
BACKGROUND OF THE INVENTION
Mixed signal integrated circuits (IC) are comprised of both digital and analog functional blocks. Digital circuits operate in switching mode and tend to generate substantial transients across the power supplies. These transients take the form of “glitches” that are superimposed upon the power and ground rails. These glitches are caused by the switched currents flowing through the supply and ground interconnects. Every piece of interconnect has a specific resistance (&Dgr;R), capacitance (&Dgr;C) and inductance (&Dgr;L), which constitute a complex impedance (Z
1
). Switched currents produce transient signals (“glitches”) across such impedance (Z
1
). While a few hundred-millivolt excursion of the power supply and ground may be inconsequential for purely digital circuits, mixed signal integrated circuits (IC) contain many analog components such as amplifiers, filters and oscillators. Such analog circuitry is substantially more susceptible to supply and ground noise. The susceptibility of the analog circuit to such noise is commonly described by the power supply rejection of the integrated circuit (IC) which describes the circuit's ability to operate under such adverse conditions.
Interaction between digital and analog circuits in mixed signal integrated circuits (IC) is mainly through common power supplies and ground connections. Other channels of interactions are through the integrated circuit (IC) substrate ties, overlapping parasitic capacitances, mutual inductances, and the like. Consequently, separation of the analog and digital supplies and/or grounds has only limited benefits because the analog and digital circuitry must eventually interface on the chip.
Supply/ground transients cause frequency jitter in the phase-locked loop (PLL) charge pump of PLL circuits within such a mixed signal integrated circuits (IC) adversely affecting the ability the PLL circuits to stay in lock. Consequently, it would be advantageous to provide a PLL charge pump capable of isolating such supply/ground transients thereby substantially diminishing the adverse effects of supply/ground glitches upon the capability of the PLL to stay in lock.
SUMMARY OF THE INVENTION
Accordingly, the present invention addresses the effect of supply/ground transients on the charge pump of PLL circuits utilized in mixed signal integrated circuits (IC) by providing a PLL charge pump capable of isolating such supply/ground transients thereby substantially diminishing the adverse effects of supply/ground glitches upon the capability of the PLL to stay in lock. In an exemplary embodiment, the PLL charge pump includes a constant current source that generates constant current source references with high power supply rejection for the P- and N-channel devices of the charge pump. Pass-gate transistors are inserted between the output terminals and the drains of the respective P- and N-channel devices. The switching transients power supply and ground are confined to the turn on/off leads of the pass-gate transistors and, thus, are isolated from the constant current source P- and N-channel devices. In exemplary embodiments of the invention, the constant current of the P- and N-channel devices may be made programmable and used for controlling the range of the current controlled oscillator of the PLL circuit.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.


REFERENCES:
patent: 5068626 (1991-11-01), Takagi et al.
patent: 5473283 (1995-12-01), Luich
patent: 5646563 (1997-07-01), Kuo
patent: 5801578 (1998-09-01), Bereza
patent: 6160432 (2000-12-01), Rhee et al.
patent: 6163187 (2000-12-01), Sano
patent: 6255872 (2001-07-01), Harada et al.

Affiliated with

Also associated with

Rating

Power rails glitch noise insensitive charge pump does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power rails glitch noise insensitive charge pump, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power rails glitch noise insensitive charge pump will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3271746