Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2002-01-15
2004-04-27
Leja, Ronald W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
06728086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to ESD (electrostatic discharge) protection technology, and more particularly, to a power-rail ESD protection circuit with a dual trigger design.
2. Description of Related Art
In the fabrication of integrated circuits (IC), such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), ESD (electrostatic discharge) usually causes damage to the IC's internal circuitry. A person who walks on a carpet under the condition of high relative humidity (RH), for example, will carry several hundreds to several thousands volts of electrostatic charge on his/her body. It can increase to more than ten thousand volts of electrostatic charge under the condition of low relative humidity. The fabrication and testing equipment in semiconductor factory, for example, will carry several hundreds to several thousands volts of electrostatic charge.
When electrostatic charge comes in contact with an IC chip, ESD will be discharged to the IC chip, consequently causing damage to the IC's internal circuitry. To prevent ESD damage to the internal circuitry, various kinds of ESD protection circuits have been proposed, such as the one shown in FIG.
1
. As shown, the NMOS
102
is connected in such a manner that its drain is connected to the power line VDD, while its gate, source, and substrate are all connected to the ground line VSS (ground line will represent VSS in the diagram). When no ESD occurs between the power line VDD and the ground line and since the gate of the NMOS
102
is connected to the ground, the NMOS
102
is in the switch-off state, thereby allowing no current leakage to flow therethrough. On the other hand, in the event of ESD between the power line VDD and the ground line, the resulted ESD voltage will be imposed on the drain of the NMOS
102
; and if this ESD voltage exceeds the breakdown voltage between the drain and substrate of the NMOS
102
, it will cause breakdown at the drain-substrate junction of the NMOS
102
and then turns on the parasitic BJT, consequently allowing the NMOS
102
to bypass the ESD current through parasitic BJT path. Therefore, the IC's device (i.e., MOS
104
) as well as the IC's internal circuitry
108
are prevented from ESD damage.
However, as IC fabrication technology advances to downsized integration, the gate oxide thickness
106
in the MOS
104
shown in
FIG. 1
are correspondingly downsized to a smaller thickness, thus reducing the breakdown voltage of their gate oxide layers
106
. If the breakdown voltage of the gate oxide layers
106
of the MOS
104
is reduced to a level substantially equal to the breakdown voltage of the junction of the ESD-bypassing NMOS
102
, it will undesirably allow the ESD voltage to breakdown the gate oxide layers
106
of the MOS
104
, thus causing damage to the MOS
104
.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a power-rail ESD protection circuit with a dual trigger design applied to the substrate and gate of the ESD-bypassing MOS device to reduce the triggering voltage needed in the parasitic BJT path in the ESD-bypassing MOS device so as to prevent ESD damage to the IC's internal circuitry, and increase ESD robustness.
The power-rail ESD protection circuit of the invention is coupled between a first power line and a second power line for protecting the IC device against ESD on the first power line and the second power line. The power-rail ESD protection circuit of the invention comprises a control circuit and at least one MOS device. The control circuit is coupled between the first power line and the second power line, and which is capable of, in the event of ESD in the first power line and the second power line, being triggered by the ESD to output a substrate-triggering voltage and a gate-driving voltage to the MOS device, causing the MOS device to bypass the ESD current from the first power line and the second power line according to the gate-driving voltage. The circuit configuration of the power-rail ESD protection circuit of the invention can help to reduce the triggering voltage needed in the parasitic BJT path and increase the ESD robustness.
REFERENCES:
patent: 6392860 (2002-05-01), Lin et al.
patent: 6455902 (2002-09-01), Voldman
Chuang Chien-Hui
Hung Kei-Kang
Faraday Technology Corp.
J.C. Patents
Leja Ronald W.
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