Power plane decoupling

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S532000

Reexamination Certificate

active

10868685

ABSTRACT:
A system and method for improved power plane decoupling. In a preferred embodiment, two dielectric layers with different dielectric constants are separated by a first conducting layer. Second and third conducting layers are positioned outside the two dielectric layers, forming a conductor-dielectric-conductor-dielectric-conductor stack. The two outer conducting layers contact each other periodically through vias made in the conducting layers, adding high dielectric constant capacitance to the plane structure for short time intervals. The lower dielectric constant material provides high propagation speed coupling to the high dielectric constant material.

REFERENCES:
patent: 6100594 (2000-08-01), Fukui et al.
patent: 6229217 (2001-05-01), Fukui et al.
patent: 6352879 (2002-03-01), Fukui et al.
patent: 6353263 (2002-03-01), Dotta et al.
patent: 6353540 (2002-03-01), Akiba et al.
patent: 2002/0085334 (2002-07-01), Figueroa et al.
patent: 2000-269407 (2000-09-01), None
U.S. Appl. No. 10/428,013, filed May 2003, Fukui et al.

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