Power overlay chip scale packages for discrete power devices

Details Power overlay chip scale packages for discrete power devices Power overlay chip scale packages for discrete power devices

1999-02-22

2001-10-23

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S107000, C438S108000, C438S109000, C438S456000, C438S617000

Reexamination Certificate

active

06306680

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to the packaging of power semiconductor devices in both single chip and multiple chip packages, with enhanced electrical and thermal characteristics.
One approach to packaging power semiconductor devices is shown in Fillion et al U.S. Pat. No. 5,637,922, wherein power semiconductor devices are mounted to a direct bond substrate, and high density interconnect (HDI) techniques are employed to form electrical connections to device top contact pads, using relatively thick copper metallization. The structures of Pat. No. 5,637,922 have the advantages of excellent thermal conductivity for carrying heat away from the bottom of the semiconductor device, the elimination of electrical parasites which would otherwise be caused by wire bond connections, reliability and robustness. Cost however is a factor, as well as the inability to mix devices of different thicknesses. In addition, it is desirable to provide semiconductor device packages which are flat on both sides, to facilitate the attachment of heat sink structures to both sides.
BRIEF SUMMARY OF THE INVENTION
In exemplary embodiments of the invention, a number of techniques are employed, including the use of pre-punched through holes, encapsulation to form substrate structures, and grinding to achieve planarization. Through-post structures are employed to alternatively bring all electrical connections either to the top side of a device package, or the bottom side. Heat sinks may be mounted to the top side, the bottom side, or both.


REFERENCES:
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patent: 5353195 (1994-10-01), Fillion et al.
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5497033 (1996-03-01), Fillion et al.
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patent: 5637922 (1997-06-01), Fillion et al.
patent: 5798286 (1998-08-01), Faraci et al.
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patent: 5841193 (1998-11-01), Eichelberge
patent: 5854085 (1998-12-01), Raab et al.
patent: 5915170 (1999-06-01), Raab et al.
patent: 6114753 (2000-09-01), Nagai et al.
patent: 6166436 (2000-12-01), Maeda et al.
patent: 6194290 (2001-02-01), Kub et al.

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