Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-02-22
2002-07-02
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S126000, C330S010000
Reexamination Certificate
active
06414614
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to power output stage compensation for digital output amplifiers.
DESCRIPTION OF THE PRIOR ART
A typical circuit for the creation of a digital data stream to drive a power output stage is a delta sigma modulator, with or without a pulse width modulator conversion stage at its output, feeding a digital output amplifier, which drives a speaker.
FIG. 1
(prior art) is a block diagram of a digital to analog converter (DAC)
100
comprising a delta sigma modulator
104
feeding a power output stage
114
into a speaker
120
. In the circuit shown in
FIG. 1
, a pulse width modulator (PWM)
108
converts the format of the data
106
from delta sigma modulator
104
. PWM
108
generates control signals
110
,
112
which feed into class D power output stage
114
. Analog power output signals
116
,
118
from class D output
114
drive speaker
120
. It is known in the art to measure the voltage of the driver output, and to use that value
122
as feedback to the delta sigma modulator
104
. This can approximately correct the loop, but some errors remain. If the distortion is due to the rise time of data pulses being smaller than the fall time, not only the area under the waveform curve is affected, but also the time delay (or higher moments) of the waveform.
The conversion to PWM is a desirable, but not necessary step. The use of PWM is preferred in many power applications, but the same comments will also apply to the direct conversion to analog of a 1 bit or multi bit delta sigma data stream.
U.S. patent application Ser. No. 09/163,235 by the present inventor (incorporated herein by reference) describes correction of systematic nonlinear output distortion that occurs in delta sigma digital to analog converters (or DACs). Feedback here is compensated feedback, as the feedback value includes the “normal” feedback term as well as the correction. U.S. patent application Ser. No. 09/457,014 by the present inventor (incorporated herein by reference) describes compensating delta sigma converters by correlating an output signal with the same signal passed through a selected nonlinear function, and correcting the output based upon the correlation.
FIG. 2
(prior art) is a block diagram of a second order one bit delta sigma converter
104
which includes separate feedback correction
242
,
244
to each of the accumulators
40
,
44
, in order to compensate for errors relating to both the area of output wave forms and delay in the waveforms. A second order delta sigma converter
104
is shown and described for simplicity, but those skilled in the art will appreciate that the same considerations apply to higher order convertors as well. Quantizer
50
is typically a multi bit quantizer in a system where it will be combined with a PWM stage. In the non-compensated case,
242
and
244
will implement unity gain functions. In second order delta sigma quantizer
104
, feedback to each accumulator is compensated for nonlinear variations in output data. If there are time effects, such as pattern generation or slew rate issues, correction block
242
and correction block
244
must implement non-trivially different functions, to account for first and second order variations. For example, one loop may be corrected, but not the other. Or, each loop may be corrected in a different manner. A non-trivial difference is where one feedback function is not a simple linear function of the other. Obviously higher moment errors can be corrected in higher order delta sigma converters with more feedback compensation. There exist many structures for the implementation of such delta sigma modulators. “Delta-Sigma Data Converters” by Norsworthy et al., IEEE Press, 1997, is a good review of the state of the art.
The inventions taught in U.S. patent application Ser. No. 09/163,235 relate specifically to correcting systematic output errors that are predictable for a given data value or series of data values. In order to compensate for unpredictable output distortion, compensation blocks
242
,
244
have to be modified in real time to properly correct for the distortion.
It is well understood that a weak link in the creation of a digital output amplifier such as class D output
114
is the imperfections of the output switches. These switches have non-zero impedance, and have rise and fall times that are significant. In addition, it is necessary to have a small dead time between the high side switch and the low side switch in order to guarantee reliable operation. Simultaneous closure of both switches will damage the system, because of the extreme current flow.
FIG. 3
(prior art) is a block diagram of a conventional class D power output stage
114
. Inputs
110
,
112
feed into dead time controls
302
,
322
, which prevent high side driver
304
from operating at the same time as low side driver
306
and prevent high side driver
324
from operating at the same time as low side driver
326
. In typical operating mode, points A and C are driven to opposite extremes, and switch
310
will be operated during the same time as switch
334
, while
314
will be operated during the same time as
330
. If the duty cycle is 50%, i.e. the two times are identical, the effective voltage delivered to the load (connected between
166
and
118
) is 0. As the duty cycle changes, the effective output voltage can be driven positive or negative.
Low side drivers
306
and
326
provide the current necessary to charge and discharge the gates of
314
and
334
. Similarly, high side drivers
310
and
330
provide drive for switching FETs
310
and
330
. The diode-capacitor network of
308
and
312
provides a bootstrapped power source for
304
. Similarly,
328
and
332
provide a power source for
324
.
The high and low drivers may have significant delays and can only charge or discharge the FET gates at a finite rate. Because of these real world limitations, the dead time control must guarantee that there is no cross-conduction. These effects give rise to the distortion that must be corrected.
FIG. 4
(prior art) is a timing diagram of signals from class D output
114
. In the example of
FIG. 4
, Signal A is high one third of the time and signal C is high two thirds of the time, resulting in filter signal B at one third level and D at two thirds level. In this case, signal A and C together average 50% on and 50% off. In some cases, it may be of value to use a modulation scheme in which the A and C signals are not mirror images of each other.
One prior art solution to the sensitivity of such a system to imperfections in the output stage switches is to carefully control the output waveforms using circuits to control the drive to the switch devices. This technique can produce acceptable results, but requires expensive analog circuitry.
A need remains in the art for apparatus and methods to correct for output distortion that is not predictable for a given value or short series of values, by either measuring the distortion and correcting it in real time or by building a model of the distortion for the system and correcting the distortion according to the model.
SUMMARY OF THE INVENTION
An object of the present invention is to compensate for distortion introduced into the output signal of a delta sigma digital to analog converter (DAC) by the power output stage of the amplifier. Such distortion is not consistent for a given output data value or short series of data values, but must be either measured and corrected in real time or must be corrected in real time based upon a sophisticated model of the system that predicts the distortion.
Apparatus for compensating for output distortion in a class D power output stage driven by a delta sigma modulator of at least second order includes means for determining distortion within the class D power output stage, means for generating a distortion signal based upon the distortion within the class D power output stage, and means for modifying at least two feedback signals in the delta sigma modulator, in non-trivially different manners, in r
Bales Esq. Jennifer L.
Cirrus Logic Inc.
Nguyen John
Shifrin Esq. Dan A.
Young Brian
LandOfFree
Power output stage compensation for digital output amplifiers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power output stage compensation for digital output amplifiers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power output stage compensation for digital output amplifiers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2836261