Power-on signal generating circuit operating with low-dissipatio

Details Power-on signal generating circuit operating with low-dissipatio Power-on signal generating circuit operating with low-dissipatio

1994-07-27

1996-06-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327198, H03K 301, H03K 5153

Patent

active

055281826

ABSTRACT:
A P-channel field effect transistor (FET) T5 is connected between a constant current circuit constituted by first and second P-channel FETs T1 and T2 and first and second N-channel FETs T6 and T7, and a resistor, and a voltage detecting circuit. A gate of the FET T5 is connected to an output of the voltage detecting circuit, a drain of which is connected to the gates of the FETs T6 and T7, and a source of which is connected to a power supply. The FET T5 operates so as to quickly start the constant current circuit when powered.

REFERENCES:
patent: 4697097 (1987-09-01), Rusznyak
patent: 4698531 (1987-10-01), Jones
patent: 4748352 (1988-05-01), Kamiya et al.
patent: 5155384 (1992-10-01), Ruetz
patent: 5243231 (1993-09-01), Baik

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