Power on reset techniques for an integrated circuit chip

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

06980037

ABSTRACT:
A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.

REFERENCES:
patent: 4588979 (1986-05-01), Adams
patent: 4746899 (1988-05-01), Swanson et al.
patent: 4851841 (1989-07-01), Sooch
patent: 4872129 (1989-10-01), Pfeifer et al.
patent: 4999626 (1991-03-01), Asghar et al.
patent: 5012245 (1991-04-01), Scott et al.
patent: 5043933 (1991-08-01), Boutaud et al.
patent: 5051981 (1991-09-01), Kline
patent: 5079734 (1992-01-01), Riley
patent: 5126695 (1992-06-01), Abe
patent: 5196810 (1993-03-01), Graether et al.
patent: 5212659 (1993-05-01), Scott et al.
patent: 5246033 (1993-09-01), Brehm et al.
patent: 5369311 (1994-11-01), Wang et al.
patent: 5446403 (1995-08-01), Witkowski
patent: 5455782 (1995-10-01), Young et al.
patent: 5513358 (1996-04-01), Lundberg et al.
patent: 5517395 (1996-05-01), Weissman
patent: 5517529 (1996-05-01), Stehlik
patent: 5539347 (1996-07-01), Duesman
patent: 5541864 (1996-07-01), Van Bavel et al.
patent: 5559458 (1996-09-01), Holler, Jr.
patent: 5608877 (1997-03-01), Sung et al.
patent: 5623234 (1997-04-01), Shaik et al.
patent: 5739708 (1998-04-01), LeWalter
patent: 5933036 (1999-08-01), Kim
patent: 6011447 (2000-01-01), Iwasaki
A. J. Stratakos et al., “High-Efficiency Low-Voltage DC-DC Conversion for Portable Applications”, IWLPD '94 Workshop Proceedings, pp. 105-110.
E.B. Hogenauer, “An Economical Class of Digital Filters for Decimation and Interpolation”, IEEE Trans. Acoust., Speech, Signal Proc., Apr. 1981, vol. ASSP-29, No. 2, pp. 155-162.
B. Leung, “The Oversampling Technique for Analog to Digital Conversion: A Tutorial Overview”, Analog Integrated Circuits and Signal Processing 1, 1991, pp. 65-74.
M. Rebeschini et al., “A High-Resolution CMOS Sigma-Delta A/D Converter with 320 kHz Output Rate”, IEEE Proc., ISCAS, 1989, pp. 246-249.
M. Alexander et al., “A 192kHz Sigma-Delta ADC with Integrated Decimation Filters Providing -97.4dB THD”, 1994 IEEE ISSCC Digest Tech. Papers, 37, pp. 190-191.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Power on reset techniques for an integrated circuit chip does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power on reset techniques for an integrated circuit chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power on reset techniques for an integrated circuit chip will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3488556

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.