Power-on reset system

Details Power-on reset system Power-on reset system

2002-10-28

2004-02-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S198000

Reexamination Certificate

active

06686783

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of power-on reset circuits, and particularly to power-on reset circuits for use in systems operated with a low supply voltage.
2. Description of the Related Art
Power-on reset circuits are well-known. Such circuits assert a reset signal, typically by toggling a digital logic signal, when a power supply voltage ramps to its rated voltage from an off state. A conventional field-effect transistor (FET) power-on reset circuit is shown in
FIG. 1
a
. A pair of transistors MP
1
and MN
1
are connected between supply voltages VDD and VSS at a node
10
, and a pair of transistors MP
2
and MN
2
are connected between the supply voltages at a node
12
. A latch
13
is also connected between VDD and VSS, formed from cross-coupled FETs MP
3
/MN
3
and MP
4
/MN
4
; the latch is controlled by the voltages applied to the gates of MN
3
and MN
4
, which are connected to nodes
10
and
12
, respectively. The output (RESET) of the circuit is taken at latch node
14
. When supply voltage VDD is less than the threshold voltage of MP
2
(Vt
MP2
), the status of node
14
is undetermined. When VDD becomes higher than Vt
MP2
, MP
2
is turned on, but MN
2
is still off. Node
12
is pulled up to the supply (VDD), which turns on MN
4
and pulls down output node
14
. An active low reset signal is generated at node
14
. When VDD further increases such that it is greater than Vt
MP1
+Vt
MN1
, node
10
is pulled up enough to turn on MN
2
and MN
3
. Since MN
2
is much stronger than MP
2
, node
12
is pulled down to VSS. The latch changes state so that the output at node
14
goes to VDD, i.e. the reset signal becomes inactive. The threshold voltage at which this occurs is referred to herein as V
dd,th
. Operation of this circuit is illustrated in
FIG. 1
b
, which plots the voltage at node
14
with respect to increasing VDD.
Unfortunately, the circuit shown in
FIG. 1
a
encounters problems when the steady-state supply voltage is low (e.g., <2.4 volts), as is increasingly common. Because the threshold voltage of a MOS transistor can vary as much as ±0.2 volts with process and ±0.2 volts with temperature, the V
dd,th
voltage, which is the sum of two MOS threshold voltages, can vary as much as ±0.8 volts. For example the V
dd,th
can range from 0.8 volts to 2.4 volts using the above power on reset circuit, setting the minimum supply voltage to 2.4 volts.
One possible example of a power-on reset circuit which could be employed with a low supply voltage is shown in
FIG. 2
a
. The circuit comprises a reference voltage generator
16
which produces a reference voltage V
ref1
as VDD ramps up from zero volts to its rated voltage, and a voltage generator
18
which produces a voltage V
2
that tracks the supply voltage. Here, V
2
=VDD−V
1
, where V
1
is the voltage drop V
be
across a p-n junction. Reference generator
16
comprises a diode connected NMOS transistor MN
5
biased by a current source i
1
, such that V
ref1
is the gate-to-source voltage (V
gs
) of an NMOS FET. A comparator
20
asserts a first reset signal RS
1
when V
ref1
is greater than V
2
, and deactivates RS
1
when V
ref1
is less than V
2
. By having V
2
vary little with process and V
ref1
compensate for changes in V
2
over temperature, the threshold voltage V
dd,th
at which RS
1
is deactivated can be controlled to ±0.2 volts of a target value with standard process variation and a wide temperature range (e.g. −40° C. to 125° C.). When properly arranged, the power-on reset circuit shown in
FIG. 2
a
can operate with supply voltages of less than 2 volts.
Unfortunately, the circuit shown in
FIG. 2
a
works well when the time (“tr”) required for VDD to ramp up is such that there is a period during the ramp up when V
ref1
>V
2
. However, when tr is too short, e.g., tr<1 ms, V
2
may remain greater than V
ref1
throughout the ramp-up time; when this happens, RS
1
is not asserted. This is illustrated in
FIGS. 2
b
and
2
c
. In
FIG. 2
b
, VDD ramps up relatively slowly. At time t
1
, currents i
1
and i
0
start up, and V
2
and V
ref1
start to increase accordingly. At time t
2
, V
ref1
becomes greater than V
2
, and RS
1
is asserted. Then, at time t
3
, V
2
becomes greater than V
ref1
and RS
1
is de-asserted. In this way, an active-low reset signal is generated, having a duration given by &Dgr;t=t
3
−t
2
.
There are two ways in which RS
1
can fail. If &Dgr;t is too short, comparator
20
may not have a chance to work and RS
1
will not be asserted. The second failure mechanism is illustrated in
FIG. 2
c
. Here, VDD ramps up so quickly that V
ref1
never becomes greater than V
2
during the ramp up time. As such, RS
1
is never asserted.
SUMMARY OF THE INVENTION
A power-on reset system is presented which overcomes the problems noted above. The present system is insensitive to the rate at which the power supply is ramped up. In addition, the power-on reset system preferably has a more precise V
dd,th
than the prior art, such that it operates reliably at a low supply voltage.
The present system includes two power-on reset circuits. The first reset circuit normally asserts a first reset signal RS
1
as VDD ramps up from zero volts to its rated voltage, as long as ramp up time tr is sufficiently long. The first reset circuit sets the threshold, V
dd,th
, for the power-on-reset system.
The second power on reset circuit is designed to assert a second reset signal RS
2
when the power-on ramp up time is short. The circuit comprises a first reference voltage generator which produces a reference voltage VR
1
as VDD ramps up from zero volts to its rated voltage, and a second reference voltage generator which produces a reference voltage VR
2
that is delayed with respect to VR
1
and is higher than VR
1
when VDD is at its rated voltage. A comparator asserts the second reset signal RS
2
when VR
1
is temporarily greater than VR
2
. A logic gate receives RS
1
and RS
2
at respective inputs, and asserts a reset signal RS
3
when either RS
1
or RS
2
is asserted; RS
3
is the output of the power-on reset system.
When so arranged, if the first reset circuit fails to assert RS
1
due to a ramp-up time which is too short, the second reset circuit asserts its reset signal RS
2
. Output reset signal RS
3
is thus asserted regardless of the duration of the ramp-up.
With the second reset circuit to overcome the short ramp-up time problem and the first reset circuit to provide a more precise V
dd,th
, the reset system can operate reliably at supply voltages of less than 2 volts.


REFERENCES:
patent: 4142118 (1979-02-01), Guritz
patent: 4902910 (1990-02-01), Hsieh
patent: 5144159 (1992-09-01), Frisch et al.
patent: 5187389 (1993-02-01), Hall et al.
patent: 5469099 (1995-11-01), Konishi
patent: 5534804 (1996-07-01), Woo
patent: 6239630 (2001-05-01), Bowers et al.
patent: 6252442 (2001-06-01), Malherbe
patent: 6437614 (2002-08-01), Chen
patent: 6492850 (2002-12-01), Kato et al.
Analog Devices,Power Supply and Watchdog Timer Monitoring Circuit, ADM9690, p. 1-6, (2000).
Analog Devices,Open-Drain Microprocessor supervisory circuit in 4-Lead SOT-143, ADM6315, p. 1-8, (2001).

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