Power-on reset signal preparing circuit

Details Power-on reset signal preparing circuit Power-on reset signal preparing circuit

2000-03-30

2002-02-12

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06346835

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power-on reset signal preparing circuit for generating a reset signal in response to the appearance of a power supply voltage. More particularly, the present invention relates to a power-on reset signal preparing circuit for generating a reset signal for resetting a main circuit in, for example, a microprocessor after a power supply voltage is stabilized after turning on of the power supply of the main circuit.
In general, most microprocessors include power-on reset signal preparing circuits for preparing reset signals in response to the appearance of their power supply voltages.
2. Description of the Related Art
FIG. 8
is a circuit diagram showing a processor which includes an example of a conventional power-on reset signal preparing circuit. In the figure, a processor
80
includes a power-on reset signal preparing circuit
81
and a main circuit
82
connected to the circuit
81
. The power-on reset signal preparing circuit
81
includes a charging circuit consisting of diodes
82
and
83
connected in series between a power supply line Vdd and the ground GND, and a pulse width preparing circuit
87
connected through inverter gates
85
and
86
to the output of the charging circuit.
FIG. 9
is a voltage waveform diagram for explaining the operation of the power-on reset signal preparing circuit
81
. As shown in the figure, due to a rise of the power supply voltage, also denoted by the symbol Vdd, from 0 volts to VH, the capacitor
84
is charged up so that the voltage at a point A rises from 0 volts. When the voltage at the point A exceeds a predetermined threshold Vth, the inverter gates
85
and
86
are enabled to operate so that a voltage at a point B rises from 0 volts to VH. The pulse width preparing circuit receives this voltage to prepare a reset pulse. This reset pulse is supplied to the main circuit
82
to reset it so as to avoid an unstable operation of the main circuit
82
during the rise of the power supply voltage.
FIG. 10
is a diagram showing an example of the conventional pulse width preparing circuit
87
. As shown in the figure, a signal from the point B is, in one hand, directly supplied to one of the inputs of an AND gate
101
, and is, on the other hand, supplied to the other of the inputs of the AND gate
101
through odd number of inverters
102
-
1
,
102
-
2
, . . . , and
102
-n. By this arrangement, a power-on reset signal having a certain width with an edge at the rise of the voltage at the point B can be obtained at the output C of the pulse width preparing circuit
87
.
In the above-mentioned conventional technique, however, when the capacity of the capacitor
84
is too small, the signal at the point A rises too fast in response to the rise of the power supply voltage so that a signal may arrive at the input of the inverter gate
85
before the next stage inverter gates are enabled to operate so that the desired edge may not be transferred to the next stage. In this case, there is a problem in that the next stage cannot prepare the reset pulse. If the capacity of the capacitor
84
is increased, the above-mentioned problem will be eliminated, however, the size of the capacitor will become large, and therefore, this tactic does not meet the requirement of miniaturizing the size of the circuit.
To avoid this, a detailed adjustment of fine circuit constants is necessary by taking the capacities of capacitors included in the circuit and the rise time of the power supply voltage into account. When the rise time of the power supply voltage takes 10 milliseconds plus several milliseconds, there is a problem in that it is difficult to form the circuit into an LSI.
In addition, since the conventional pulse width preparing circuit must generate a delay by using a large number of stages of inverter gates, there is a problem in that a large physical area is necessary. Still further, when the polarity of the pulse signal must be changed, the circuit design must also be changed, so that there is a problem in that the circuit lacks flexibility. Still further, since the delay times in the gates vary depending on the manufacturing conditions, there is a problem in that the pulse width of the power-on reset signal also varies depending on the various delay times.
SUMMARY OF THE INVENTION
In view of the above problems in the prior art, an object of the present invention is to provide a power-on reset signal preparing circuit which can surely prepare a reset pulse even when a capacitor of a small size is used.
Another object of the present invention is to provide a power-on reset signal preparing circuit which requires a small physical area, does not require a circuit for changing the polarity of the pulse signal, and has a pulse width preparing circuit with a small variation of the pulse width.
To attain the above objects, there is provided, according to the present invention, a power-on reset signal preparing circuit comprising two charging circuits having different charging times when the same power supply voltage is applied, a driving circuit for outputting a driving voltage based on the output voltages from the two charging circuits, and a pulse width preparing circuit for generating a reset pulse to reset a main circuit based on the driving voltage output from the driving circuit.
Since the pulse width preparing circuit is driven based on the output voltage from the two charging circuits, the reset pulse is surely generated and the capacities of the capacitors constructing the two charging circuits may be small. Therefore, the power-on reset signal preparing circuit according to the present invention meets the requirement regarding the size of the circuit.
According to one aspect of the present invention, the driving circuit is a switching means which is turned on to supply a driving voltage to the pulse width preparing circuit when the difference between the output voltages from the two charging circuits exceeds a predetermined value after applying a power supply voltage to the power-on reset signal preparing circuit.
According to another aspect of the present invention, the driving circuit is a gate means which supplies a driving voltage to the pulse width preparing circuit when both of the output voltages from the two charging circuits reach a predetermined threshold after applying a power supply voltage to the power-on reset signal preparing circuit.
According to still other aspect of the present invention, the pulse width preparing circuit is formed by two wiring lines connected to the output of the driving circuit and to the earth and running substantially parallel to each other.
By changing the length of the parallel lines, the area required for the pulse width preparing circuit may be smaller than that in the case of forming the pulse width preparing circuit by gates.


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patent: 4142118 (1979-02-01), Guritz
patent: 5144159 (1992-09-01), Frisch et al.
patent: 5214316 (1993-05-01), Nagai
patent: 5677643 (1997-10-01), Tomita
patent: 5770959 (1998-06-01), Hopkins et al.
patent: 5929674 (1999-07-01), Maccarrone et al.
patent: 6087866 (2000-07-01), Prucklmayer
patent: 4-179183 (1992-06-01), None
patent: 8-036442 (1996-02-01), None
patent: 9-307416 (1997-11-01), None

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