Power on reset signal circuit with clock inhibit and delayed res

Details Power on reset signal circuit with clock inhibit and delayed res Power on reset signal circuit with clock inhibit and delayed res

1994-02-04

1995-08-29

Westin, Edward P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327398, 326 94, H03K 3014

Patent

active

054464030

ABSTRACT:
A control circuit inhibits the CLOCK input to the CPU during power-up to prevent newer submicron CPUs from locking up during a power-up condition. The control circuit also provides a delayed control signal representing that the power supply has stabilized. This delayed control signal is used to consistently control the RESET signal.

REFERENCES:
patent: 4558233 (1985-12-01), Nakamori
patent: 4641044 (1987-02-01), Shiraishi
patent: 4933902 (1990-06-01), Yamada et al.
patent: 4940909 (1990-07-01), Mulder et al.
patent: 5212412 (1993-05-01), Atriss et al.
patent: 5323066 (1994-06-01), Feddeler et al.
patent: 5343085 (1994-08-01), Fujimoro et al.

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