Power-on reset pulse generator

Details Power-on reset pulse generator Power-on reset pulse generator

1984-01-16

1986-05-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307594, 307597, H03K 1722, H03K 1720, H03K 17687, H03K 5153

Patent

active

045917450

ABSTRACT:
A circuit for generating a pulse is disclosed for resetting certain multi-state elements of an electronic system after the power supply of the system has been activated and said elements have settled. The circuit is composed of an R-C network and a latch. The latch is activated by the power supply and it sets its output to a preselected state. The latch switches to a second state after a capacitor of the RC network is charged to a preselected level. The output of the latch is used to derive the reset signal. The reset signal may be delayed by a delay circuit and amplified and buffered or conditioned by an amplifying stage. The circuit is comprised of elements which may be produced by IC techniques such as CMOS so that it may be implemented on a single IC chip.

REFERENCES:
patent: 3895239 (1975-07-01), Alaspa
patent: 4140930 (1979-02-01), Tanaka
patent: 4260907 (1981-04-01), Winebarger
patent: 4307306 (1981-12-01), Kucharewski
patent: 4365174 (1982-12-01), Kucharewski
patent: 4385245 (1983-05-01), Ulmer
patent: 4405871 (1983-09-01), Buurma et al.
patent: 4419596 (1983-12-01), Kikuchi
patent: 4533837 (1985-08-01), Tanaka et al.

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