Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-06-03
2004-01-27
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
Reexamination Certificate
active
06683481
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to Programmable Logic Devices (PLDs). More particularly, the invention relates to a power on reset circuit for a PLD that provides hysteresis in a noisy power environment.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g. DLLs, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
In each of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory or E-squared memory, as in some CPLDs), or in any other type of memory cell.
Every PLD, whatever its type, must at some point be “powered up”, i.e., awakened from a zero power state to a point at which the power high voltage VDD reaches an acceptable operating voltage level. The power up reset sequence resets the PLD so the device will function properly. For example, during the power up reset sequence, the input/output (I/O) pins of the PLD are preferably tristated (i.e., no signal is applied to the output pins by the PLD logic), the internal memory cells are initialized, and a configuration state machine is initialized and made ready to configure the part with the configuration data provided to the device.
Once the power high voltage VDD is high enough for the transistors of the device to operate properly, the configuration state machine takes control of the configuration process and begins loading configuration data into the volatile memory cells. When all of the data has been loaded, the I/O pins are enabled, and the device is ready to begin performing its programmed functions.
Another reset process takes place when a device is powered down, i.e., the power high voltage VDD is brought from the operating voltage level back down to the zero power state (or below a triggering voltage level). During the power down reset sequence, the PLD detects that the power high voltage VDD has reached or is nearing an unacceptably low level and performs a sequence of operations such as saving current state information, informing other integrated circuits (ICs) to stop sending data to the PLD, and so forth.
The power up and power down reset procedures are complicated by the fact that power supplies can be “noisy”, i.e., glitching significantly above and/or below the nominal voltage level. For example, during the power up sequence, VDD can rise above the acceptable level and then fall below this level one or more times before reaching the final operating voltage. Additionally, once at the operating voltage, VDD can glitch to below a power down triggering voltage. Similarly, during the power down sequence, VDD can fall below the acceptable level and then rise back above this level one or more times before reaching the zero power level. Therefore, it is desirable to provide hysteresis (i.e., protection against transmitting such glitches) to circuitry that controls the power-related reset functions in a PLD.
FIG. 1
shows exemplary power up and power down voltage levels for VDD and corresponding voltage levels on a power on reset signal called POR. When signal POR is high, the device undergoes a reset process as described above. Note that in this example the POR signal is active-high, although power on reset signals can be either active-high or active-low. When used as a signal name herein, the name “POR” indicates an active-high signal, while the name “PORB” is used for an active-low signal. However, when used as an adjective, the acronym POR is simply used as an abbreviated form of the phrase “power on reset”.
As shown in
FIG. 1
, when VDD begins to ramp up from the zero volt power level, VDD first reaches a level called VCMOSmin (time T
0
). VCMOSmin is the minimum power high level at which CMOS logic will function. At the VCMOSmin power level, the POR signal changes to a high value and the PLD enters reset mode. Because the power to the POR signal generator is provided by VDD, the voltage level of POR tracks VDD and does not exceed VDD at any given time.
The voltage level of VDD (and the POR signal) rises past the voltage level VOPmin, which is the minimum voltage at which all of the PLD circuitry will operate. Because not all of the logic in the PLD is digital CMOS logic, VOPmin is higher than VCMOSmin. VDD and POR then continue to rise to the voltage level called VPOR (time T
1
). At voltage level VPOR, the PLD is considered to be successfully reset and the POR signal is removed (i.e., the active-high signal POR goes low again). The PLD loads the configuration data from non-volatile memory, then enters user mode, i.e., begins to performs its programmed functions. The applied voltage VDD continues to rise until it passes the specified minimum operating voltage, SpecVDDmin.
FIG. 1
also shows the consequences of glitches on the VDD power level. If VDD glitches down while the PLD is in operating mode, but does not fall below the VPOR voltage level (e.g., at times T
2
and T
3
), the power on reset circuitry is not affected and the PLD continues to operate in user mode. If VDD glitches below the VPOR voltage level, as at time T
4
, the POR signal is forced high and the PLD goes through the reset sequence again.
The POR signal must remain high long enough for the power on reset sequence to be successfully concluded. In the example of
FIG. 1
, duration D
1
between times T
0
and T
1
is long enough to complete the reset sequence. Similarly, duration D
2
after time. T
4
is long enough to complete the reset sequence. However, after time T
5
there are several glitches that restart the reset sequence repeatedly until (after time T
6
) there is finally a duration D
3
that is sufficient to successfully reset the PLD.
At time T
7
, the VDD power high voltage level falls below the VPOR power level, and signal POR is driven high. The power down reset sequence is initiated. Signal POR then follows power high VDD down to below the VCMOSmin power level (time T
8
), at which point signal POR goes low again. Note that in the example of
FIG. 1
the triggering voltages for both rising and falling power levels are the same (VPOR). These power levels can be the same or different from each other.
A noisy power environment is a greater problem for PLD designers and users than was previously the case, because PLD operating voltages are lower than they used to be. Thus, the difference between the operating voltage and the threshold voltage of an N-channel transistor, for example, is decreasing. A “glitch” that can inadvertently change the state of a memory cell, for example, can more easily occur with a lower operating voltage. Threshold voltag
Nguyen Andy T.
Zhou Shi-dong
Cartier Lois D.
Xilinx , Inc.
Zweizig Jeffrey
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