Power-on reset circuit with arbitrary output prevention

Details Power-on reset circuit with arbitrary output prevention Power-on reset circuit with arbitrary output prevention

1992-07-08

1994-05-03

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072964, 377114, G06F 1100

Patent

active

053090373

ABSTRACT:
A power-on reset circuit is used to initialize a system component upon power-on. The circuit comprises a digital circuit such as a shift register which exhibits a multiplicity of uncertain or random outputs upon power-on. These output are coupled to digital logic such as an AND gate which itself outputs a power-on reset signal when any of the outputs of the shift register is not a predetermined output level. Because the outputs of the shift register are uncertain or arbitrary upon power-on and there are a multiplicity of such outputs, it is not likely that all of the outputs of the shift register will coincidentally exhibit the predetermined levels upon power-on. Consequently, it is very likely that the AND gate will provide the power-on reset signal upon power-on to initialize the system component. Subsequently, when the system is ready for normal operation, the shift register is set with the predetermined levels to terminate the power-on reset signal and thereby enable or condition the system component for normal operation.

REFERENCES:
patent: 4551841 (1985-11-01), Fujita et al.
patent: 4608669 (1986-08-01), Klara et al.
patent: 4983857 (1991-01-01), Steele
patent: 4989175 (1991-01-01), Boris et al.
patent: 5039875 (1991-08-01), Chang
IBM TDB, vol. 34, No. 3, Aug. 1991, B. K. Bullis et al., pp. 448-451, "Asynchronous Reset Control of LSSD Parts".

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