Static information storage and retrieval – Powering
Reexamination Certificate
2000-10-23
2001-11-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
C365S194000, C365S207000
Reexamination Certificate
active
06314040
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to reset circuits generally and, more particularly, to a power-on-reset circuit with analog delay and high noise immunity.
BACKGROUND OF THE INVENTION
Many POR circuits have a supply detector that effectively decides whether the POR signal is asserted. This detector will assert a control signal at power up of the device. This detector may also assert the control signal if the supply voltage undergoes a major transition such as a glitch. The responsibility for the POR signal is thus in the domain of the detector, and the detector is designed to switch under adverse (but defined) conditions.
In order to add a delay (or “timeout”) to the POR circuit to extend the duration of the POR signal, one should ensure that the delay circuit does not override the detector. The delay circuit should therefore be more noise immune/tolerant than the detector. Otherwise, the POR signal may be asserted under inappropriate conditions.
In U.S. Pat. No. 5,477,176 (to Chang et al.), the delay circuit has little or no supply noise immunity. Furthermore, it does not appear to be possible to reset the delay circuit in response to a supply glitch (reset condition). This may be a consequence of the lack of feedback circuitry in the POR circuit. The POR circuit of Chang et al. appears to be highly susceptible to supply noise, whereby the delay circuit may cause a full and unwanted transition in the POR output. The detector is thus not dominant, and the delay circuit will not be reset when the detector fires. Once the capacitor is charged, a transition on the detector output does not enforce a discharge.
In U.S. Pat. No. 5,602,502 (to Jiang), it also does not appear to be possible to reset the delay circuit in response to a supply glitch (reset condition). This may also be a consequence of the lack of feedback circuitry in the POR circuit of Jiang. However, Jiang's circuit has some delay circuit noise immunity since the delay circuit is latched off when the POR is complete. The delay capacitor element is not reset, however, hence a full duration POR signal may not be effected. In systems such as that of Jiang, the duration of the POR signal typically depends on the rate at which the capacitor discharges, since it is not actively discharged.
In U.S. Pat. No. 5,302,861 (to Jelinek), the POR circuit contains neither a delay circuit nor a feedback element. This circuit has two capacitors, which appear to be used for decoupling, rather than for a delay.
U.S. Pat. No. 5,557,579 (to Raad et al.) discloses a delay circuit, which appears to have little or no supply noise immunity or feedback. Functionally, Raad et al. describe a POR circuit. Two such circuits are actually described since within the text of this patent. A reference is made to an alternative circuit where the detector controls the delay circuit. However, the delay circuit appears to offer little or no noise immunity, and therefore, may be susceptible to unwanted resetting. This is exacerbated by the fact that the POR state is not latched. The POR circuit of Raad et al. is targeted at a DRAM application where the POR indicates when the memory element state is valid. However, there is no feedback from the memory element to indicate when it is valid. The delay must be carefully chosen to meet or exceed the time required for that device or that size of memory.
SUMMARY OF THE INVENTION
The present invention concerns a power-on-reset circuit that may be configured to present a power-on-reset signal in response to a voltage. The power-on-reset circuit may comprise a voltage detector, a first analog delay circuit and a feedback loop. The first analog delay circuit may be coupled to an output of the voltage detector. The feedback loop may be coupled an output of the power-on-reset circuit to an input of the power-on-reset circuit.
The purpose of this invention is to provide a power-on-reset circuit that incorporates an analog delay element yet retains relatively high noise immunity.
Another purpose of this invention is to provide a power-on-reset circuit in which the noise immunity is dominated by an operating voltage detector.
These and other purposes, objects and advantages of the invention, which will become apparent from reading the following detailed description of the invention, will be discussed in greater detail in the following sections.
Conventionally, power-on-reset circuits should exhibit high noise immunity to supply disturbance. Introducing analog delay element(s) into such circuits is detrimental to that noise immunity.
Within the power-on-reset (POR) circuit, a detector may be present to distinguish circumstances and/or conditions where resetting the circuitry affected and/or controlled by the POR circuit is appropriate. Other elements within the POR circuit should continue to be functional in these circumstances, thus suggesting that the detector remain dominant.
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Cypress Semiconductor Corp.
Le Thong
Maiorana P.C. Christopher P.
Nelms David
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