Power-on reset circuit for preventing multiple word line selecti

Details Power-on reset circuit for preventing multiple word line selecti Power-on reset circuit for preventing multiple word line selecti

1994-06-02

1995-12-19

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327142, 327198, 327513, H03L 700

Patent

active

054771765

ABSTRACT:
A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

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