Power-on-reset circuit for generating a reset signal to reset a

Details Power-on-reset circuit for generating a reset signal to reset a Power-on-reset circuit for generating a reset signal to reset a

1998-11-19

2000-08-29

Elms, Richard

Static information storage and retrieval

Powering

36518909, G11C 700

Patent

active

061118052

ABSTRACT:
In a signal generating circuit generating a reset signal for resetting a DRAM at the time of turning on the power supply potential, a resistance element is connected between a line of the power supply potential and a node, and two N channel MOS transistors constituting a discharge circuit are connected in series between the node and a line of a ground potential. When the power supply potential is lower than a prescribed potential, the two N channel MOS transistors are rendered non-conductive so that the node attains to the "H" level, and when the power supply potential is higher than the prescribed potential, the two N channel MOS transistors are rendered conductive so that the node attains to the "L" level. Therefore, even when the power supply potential changes moderately, the level of the reset signal changes abruptly, surely resetting the DRAM.

REFERENCES:
patent: 5278792 (1994-01-01), Inoue et al.
patent: 5436586 (1995-07-01), Miyamoto
patent: 5652730 (1997-07-01), Kono et al.
patent: 5703804 (1997-12-01), Takata et al.
patent: 5870342 (1999-02-01), Fukuda
"A 4Mb Pseudo SRAM Operating at 2.6+-1V With 3uA Data Retention Current", K. Sato et al., 1991 IEEE International Solid-State Circuits Conference pp. 268-269.

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