Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-04-19
2002-01-01
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06335646
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Japanese Patent Application No. No. 11-123131, filed Apr. 28, 1999, the entire subject matter of which is incorporated herein of reference.
BACKGROUND OF THE INVENTION
1. Field of the invention
The invention relates to a power-on reset circuit, more particularly, to a circuit that outputs a pulse to reset an internal circuit of a semiconductor device upon detection that power supply has turned on.
2. Description of the Related Art
FIG. 2
shows a first power-on reset circuit in the related art. The first power-on circuit includes a resistor
1
, a capacitor
2
and an inverter
3
. One end of the resistor
1
is connected to a power supply line to which a power supply voltage Vdd is applied. The capacitor
2
is connected between the other end of the resistor
1
(a node N
1
) and ground. An input terminal of the inverter
3
is connected to the node N
1
.
FIG. 3
is a timing chart showing operational waveforms of the first power-on reset circuit shown in FIG.
2
. The operations of the first power-on reset circuit is explained with reference to FIG.
3
. When the power supply voltage Vdd is applied to the power supply line, an electric current flows through the resistor
1
so that the capacitor
2
is charged. When the power supply voltage Vdd goes up, the voltage at the node N
1
goes up to Vdd with delay determined by a time constant which is decided by the resistor
1
and the capacitor
2
. Since the inverter
3
is activated by the power supply voltage Vdd, a threshold voltage Vti of the inverter
3
goes up in proportion to the increase of the power supply voltage Vdd. As the voltage at the node N
1
is lower than the threshold voltage Vti of the inverter
3
just after the power supply voltage Vdd is applied to the circuit, the inverter
3
outputs an H level signal having a voltage that goes up similar to the power supply voltage Vdd. At a time T
1
, the voltage of the node N
1
exceeds the threshold voltage Vti of the inverter
3
, and the inverter outputs an L level signal. According to the operation mentioned above, the inverter
3
outputs a signal as a reset pulse signal P. The reset pulse signal P is applied to reset internal circuits of a semiconductor device.
FIG. 4
shows a second power-on reset circuit in the related art. The second power-on circuit includes a resistor
4
, an NMOS transistor
5
, a first inverter
6
and a second inverter
7
. One end of the resistor
4
is connected to a power supply line to which a power supply voltage Vdd is applied. The NMOS transistor
5
includes a source which is connected to ground, a drain which is connected to the other end of the resistor
4
(a node N
2
), and a gate which is connected to the power supply line. An output terminal of the first inverter
6
is connected to an input terminal of the second inverter
7
. An input terminal of the first inverter
6
is connected to the node N
2
.
FIG. 5
is a timing chart showing operational waveforms of the second power-on reset circuit shown in FIG.
4
. The operations of the second power-on reset circuit is explained with reference to FIG.
5
. When the power supply voltage Vdd is applied to the power supply line and the power supply voltage Vdd goes up, the voltage at the node N
2
also goes up. At a time T
2
, the power supply voltage Vdd reaches to a threshold voltage Vtn of the NMOS transistor
5
. At that time, the NMOS transistor turns on and the voltage at node N
2
turns to go down. At a time T
3
, the voltage at node N
2
is equal to a threshold voltage Vti of the first inverter
6
. Therefore, the output signal of the first inverter
6
turns from a L level to an H level. That is, until the time T
3
, the first inverter
6
outputs the L level signal having ground level and the second inverter
7
outputs the H level signal having a voltage that goes up similar to the power supply voltage Vdd. After the time T
3
, the second inverter
7
outputs the L level signal and the first inverter
6
outputs the H level signal having a voltage that goes up similar to the power supply voltage Vdd. According to the operation mentioned above, the second inverter
7
outputs a signal as a reset pulse signal P. The reset pulse signal P is applied to reset internal circuits of a semiconductor device.
When the power supply voltage Vdd gradually goes up the voltage at the node N
1
also goes up gradually. Specifically, when the voltage at the node N
1
comes close to the threshold voltage of the inverter
3
, the inverter
3
of the first power-on reset circuit may output the H level signal and L level signal repeatedly. As a result, the wave form of the reset pulse signal of the first power-on reset circuit may be unstable.
When the power supply voltage goes up rapidly, the NMOS transistor
5
of the second power-on reset circuit may turn on just after the power is applied to the circuit. Accordingly, the first inverter
6
may output the H level signal because the electric potential at the node N
2
rapidly falls to the grand level, and the second inverter
7
may continuously output the L level signal. Thus, the reset pulse signal of the second power-on reset circuit may not be generated.
SUMMARY OF THE INVENTION
An objective of the invention is to provide a power-on reset circuit for outputting a stable reset pulse signal regardless of a rising speed of a power supply voltage. That is, the power-on reset circuit of the invention can output a reset pulse signal when the power supply goes up either gradually or rapidly.
The objective is achieved by a power-on reset circuit generating a reset pulse upon detection of a power supply voltage. The circuit comprises a resistor connected between a power supply line to which a first power supply potential is applied and a first node, a first transistor having a gate connected to the power supply line, a drain connected to a second node, and a source connected to a reference node to which a second power supply potential is applied, a second transistor having a gate connected to the power supply line, a drain connected to the first node, and a source connected to the second node, a capacitor connected between the second node and the power supply line or the reference node, and an inverter having an input terminal connected to the first node.
REFERENCES:
patent: 4551841 (1985-11-01), Fujita et al.
patent: 4581552 (1986-04-01), Womack et al.
patent: 4812679 (1989-03-01), Mahabadi
patent: 4970408 (1990-11-01), Hanke et al.
patent: 4985641 (1991-01-01), Nagayama et al.
patent: 5180926 (1993-01-01), Skripek
patent: 5847586 (1998-12-01), Burstein et al.
patent: 6121803 (2000-09-01), Tanaka
patent: 6204701 (2001-03-01), Tsay et al.
patent: 58-80928 (1983-05-01), None
Cunningham Terry D.
Mimura Juichi
Oki Electric Industry Co. Ltd.
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