Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-07-14
2001-04-10
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06215342
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuitry for generating power-on reset signals for transmission to integrated circuit systems. In particular, the present invention relates to a power-on reset circuit that operates to hold off power-on reset until the high-potential power supply rail reaches a defined potential. More particularly, the present invention relates to power-on reset circuitry that operates as required when coupled to circuitry powered by supplies of differing potentials. The present invention is a power-on reset circuit used in association with logic level translation systems.
2. Description of the Prior Art
Power-on reset circuits are designed to transmit to semiconductor-based systems signals to enable operation of such systems only when a common high-potential power rail reaches a certain minimum potential. These power-on reset circuits may be used to enable “hot” or live insertion of systems or subsystems such as circuit boards that are initially unpowered into extended coupled circuitry that is powered. The power-on reset circuitry is supposed to protect the unpowered system or subsystem from significant initial potential variations that may cause damage or unexpected operational anomalies in the circuitry that is inserted into the active system. In effect, the power-on reset circuit is designed to hold off enabling activation of the subsystem until the power rail potential is suitable for activation of that particular subsystem.
A voltage level converter or translator buffer is used to adjust the logic high and logic low voltage levels associated with a single input signal, or a pair of input signals, coming into the buffer to high and low voltage levels compatible with downstream circuitry. The translator buffer must transfer these electrical signals at desired amplitude and rate and, preferably, using as little power as possible. The signal transfer occurs between active devices that are either on the same semiconductor-based chip or on different chips. The devices may be located proximate to one another, or they may be some distance from one another. One example of a proximate device interface requiring one or more bus connections is the coupling of one printed circuit board to another within a computing system, such as through a backplane bus. An example of a remote device interface requiring one or more bus connections is the coupling of one computing system to another.
It is well known that in digital systems the signals moving between devices are categorized as either logic level high (or “1” or “ON”) and logic level low (or “0” or “OFF”). The particular signal potential that defines whether a logic high or a logic low is being transmitted is dependent upon the semiconductor components that form the circuitry associated with that transmission. The most common circuit configurations used to produce digital signals include, among others, CMOS, Transistor-Transistor Logic (TTL), and Emitter Coupled Logic (ECL). Each of these logic configurations operates differently as a function of the “swing” between what constitutes a logic high signal and what constitutes a logic low signal.
For CMOS logic systems for example, which is based primarily on the use of slower, less-power-consuming MOS transistors, a logic low signal is generally developed in the range of 0.6 volts (V) above a low-potential power rail GND, which may be at 0.0 V. A logic high signal is generally developed in the range of Vcc to Vcc-0.6 V, where Vcc may vary between 4.5 V and 5.5 V for a nominal 5-volt supply, or between 3.0 V and 3.6 V for a nominal 3.3-volt supply. For the 3.3-volt supply then, the differential swing between low and high must be at least 2.4 volts in order to ensure that a desired shift between a logic low and a logic high will occur. More recently, nominal 2-volt supplies are being used to power eversmaller devices. TTL and ECL logic configurations, on the other hand, are based primarily on the use of faster, high-power-consuming bipolar transistors. The differential swing for a shift between a logic low and a logic high is significantly less than it is for CMOS operation—it may as low as 0.4 volt. In TTL circuitry for example, which is Vcc dependent, a logic high is equivalent to a potential of about Vcc-0.8 V and a logic low is equivalent to a potential of about Vcc-1.9 V. Thus, in mating CMOS and non-CMOS transmissions, it can be seen that variations in potential swings will not automatically ensure the triggering of a desired swing from one logic level to another. Furthermore, minor potential swings in TTL signals, and low voltage TTL (LVTTL) swings in particular, may not effect any logic level change associated with CMOS transistors connected thereto. Alternatively, signal swings that do not reach full CMOS potentials, whether high or low, or that at least do so relatively slowly, can cause both pull-up (P-type MOS) transistor and pull-down (N-type MOS) transistor to be on at the same time. This produces a direct rail-to-rail current flow through the on PMOS and NMOS transistors. This current is known as simultaneous conduction current or leakage current and is an undesirable source of power consumption.
Power-on rest circuits come in a variety of designs. One circuit that has been found to be adequate in prior systems requiring the translation of a reset signal at one potential to a signal at a higher potential is illustrated in a simplified diagram in FIG.
1
. The prior reset circuit with translation
10
shown includes a first reset sub-circuit
20
powered by first high-potential power rail Vcca at a first potential, and a second reset sub-circuit
30
powered by a second high-potential power rail Vccb at a second potential higher than the first potential of Vcca. A simple logic-level translator sub-circuit
40
increases the potential associated with reset sub-circuit
20
to that associated with reset sub-circuit
30
to enable appropriate interfacing of the reset sub-circuit
20
with the reset sub-circuit
30
and following circuitry coupled thereto. An exemplar suitable translator sub-circuit is shown in FIG.
2
. The translated output signal at output node B is one input to any sort of logic gate capable of controlling the state of the output of circuit
10
including, for example, logic NOR gate NOR. The output of inverter IV
4
is the other input to NOR. When potentials of circuits
20
and
30
have exceeded some defined value set, the outputs of
40
and IV
4
are both low and the power-on reset signal is activated in that RESET will be a logic high at the potential of Vccb.
With continuing reference to
FIG. 1
, sub-circuit
20
includes a voltage divider formed of resistors R
1
and R
2
, wherein R
1
has a high-potential node coupled to high-potential power rail Vcca and R
2
has a low-potential node coupled to a common low-potential power rail GND. Resistor R
3
coupled in series with NMOS transistor Ml acts as an inverter, wherein the high-potential node of R
3
is coupled to Vcca and its low-potential node is coupled to the drain of Ml. Ml has its source coupled to GND and its gate coupled to the output of the voltage divider R
1
/R
2
. As the potential of Vcca ramps up, it reaches some level defined by the voltage divider at which the output of inverter R
3
/M
1
flips from a logic high to a logic low. That output signal is twice inverted at full Vcca potential by inverters IV
1
and IV
2
such that the output of IV
2
at node A is the equivalent of a logic low when Vcca reaches full potential. It is to be noted that other switching means may be used as a substitute for transistor Ml, including, for example, a bipolar transistor.
Sub-circuit
30
is similarly configured. Specifically, sub-circuit
30
includes a voltage divider formed of resistors R
4
and R
5
, wherein R
4
has a high-potential node coupled to high-potential power rail Vccb at a first potential, and R
5
has a low-potential node coupled to GND. Resistor R
6
coupled in series with NMOS transistor M
2
acts as an inverter,
Atwood Pierce
Caseiro Chris A.
Fairchild Semiconductor Corporation
Tran Toan
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