Power-on reset circuit

Details Power-on reset circuit Power-on reset circuit

2003-03-18

2004-06-08

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S198000

Reexamination Certificate

active

06747493

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power-on reset circuit, and more particularly to a power-on reset circuit which generates a power-on reset signal when power supply to an apparatus is turned on.
2. Description of the Related Art
A power-on reset circuit would be installed for one or the other of two purposes. One is to initialize circuits when power supply to an apparatus is turned on. The other is to extend a reset signal to prevent, in a digital communication apparatus having a rack configuration, unstable operations of the power supply system and the clock line when each package power supply is actuated at the time of live insertion or extraction from sending abnormal signals to a signal line shared by a plurality of packages via a mother board in the apparatus. A reset extending circuit might also be used for extending to a certain extent the length of time from actuating power supply to release of the reset to stabilize the operation of integrated circuits.
Whereas the action at the time of actuating power supply differs from circuit to circuit depending on the circuit configuration, it is desirable to have available a power-on reset circuit which need not be adjusted to match the difference in action and, while the lengths of time taken to actuate power supply, to start the clock output and to achieve stability differ every time, the power-on reset circuit is desired to be able to initialize the circuits securely by a power-on reset.
According to the prior art, a power-on reset extending circuit shown in
FIG. 6
is used as a synchronous circuit. In
FIG. 6
, a reset extending circuit
31
is supplied with an external power-on reset signal POWRSTB via an inverter
32
. If a clock signal CLK is inputted to a clock terminal when the logical value of that input signal POWRSTB via an inverter
32
is “H”, the reset extending circuit
31
supplies from an inverter
33
a signal RSTB of “L” in logical value, extended for a prescribed length of time.
However, depending on the timing at which power supply is turned on, the output signal RSTB shown in FIG.
7
(D) may fail to, vary, remaining at the value of “H”. This would occur when, as shown in FIG.
7
(C), the external power-on reset signal POWRSTB is supplied to the reset extending circuit
31
via the inverter
32
and, after the logical value of that input signal has varied to “L” (that of the POWRSTB signal is “H”), the clock signal CLK is inputted to the clock terminal as shown in FIG.
7
(B).
Thus the reset extending circuit
31
, in a situation in which the input of the clock signal CLK is suspended when a power-on reset signal is asserted, cannot detect the input of the power-on reset signal POWRSTB and accordingly cannot extend the reset signal. In such a case, abnormal signals may be transmitted to a signal line shared by a plurality of packages or the operation of the integrated circuits into which the output signal RSTB is entered may be destabilized. Incidentally, FIG.
7
(A) shows a source voltage VCC, in response to whose actuation the output signal RSTB also varies to the “H” level as shown in FIG.
7
(D).
In contrast to the foregoing, as described in the Japanese Patent Application Laid-open No. Hei 8-63264, a power-on reset circuit according to the prior art shown in
FIG. 8
can reliably detect a power-on reset even if the input of a clock CLK is suspended while a power-on reset signal POWRSTB is being asserted. Thus, referring to
FIG. 8
, the clock signal CLK is supplied in common to the clock terminals of D type flip-flops (D-FFs)
431
through
43
n
which are cascade-connected in n stages via an inverter
41
. The “H” level is constantly supplied to the D-FF
431
of the first stage all the time. The Q output signal of the D-FF
43
n
of the final stage is supplied to an AND gate
44
, and its logical product of multiplication by an external power-on reset signal POWRSTB is supplied to a reset extending circuit
45
.
In this power-on reset circuit according to the prior art, immediately after the turning-on of power supply raises the source voltage VCC to the “H” level as shown in FIG.
9
(A), the external power-on reset signal POWRSTB rises to the “H” level as shown in FIG.
9
(C) and is commonly supplied to the clear terminals of the D-FFs
431
through
43
n
via an inverter
42
to initialize them, and after that a clock signal CLK is entered as shown in FIG.
9
(B). Then, every time the clock signal CLK rises and is entered, the “H” level supplied to the D input terminal of the D-FF
431
of the first stage is successively transferred to the D-FF of the next stage, the Q output signal of the D-FF
43
n
of the final stages stays at the “H” level from the point of time when n clock signals CLK have risen and been entered (the point of time when n clock cycles Tn have passed since the input time of the first clock signal CLK as shown in FIG.
9
), and signals of the “H”. level are outputted from the AND gate
44
to be supplied to the reset extending circuit
45
.
The reset extending circuit
45
counts the clock signals CLK supplied via the inverter
41
as long as the signals of the “H” level are supplied from the AND gate
44
and, when a predetermined number has been counted (when a period Tr has passed after the lapse of the aforementioned period Tn), supplies the output signal RSTB of the “H” level as shown in FIG.
9
(D). This power-on reset circuit according to the prior art can supply the output signal RSTB of a prescribed level at a point of time when the aforementioned period (Tn+Tr) has passed since the first input of the clock signal CLK even if any clock signal CLK is entered after the input of the external power-on reset signal POWRSTB.
However, while the power-on reset circuit according to the prior art shown in
FIG. 8
above has a configuration in which the external power-on reset signal POWRSTB is delayed by n clock cycles Tn by using the D-FFs
431
through
43
n
which are cascade-connected in n stages, it is not confirmed whether or not this external power-on reset signal POWRSTB delayed by n clock cycles Tn is detected without fail by the reset extending circuit
45
of the next stage.
For this reason, even if the power-on reset circuit according to the prior art shown in
FIG. 8
above permits elongation of the aforementioned delay time Tn by increasing the number n of the D-FFs, the characteristics of the following reset extending circuit
45
should be judged and adjustment be made accordingly, and this inevitably requires pertinent know-how.
An object of the present invention, attempted in view of the problems noted above, is to provide a power-on reset circuit capable of releasing the power-on reset after it has been confirmed that a reset extending circuit has detected a power-on reset signal without fail and without having to add otherwise unnecessary flip-flops and to adjust them.
Another object of the invention is to provide a power-on reset circuit capable of making available a stable system which would not supply any abnormal signal to a common signal line and be free from erroneous operation as an apparatus of a rack configuration.
SUMMARY OF THE INVENTION
In order to achieve the objects stated above, a power-on reset circuit according to the invention comprises an input circuit which is initialized by the assertion of a power-on reset signal entered from outside when power supply is turned on and supplies a first signal of a first logical value at the time a detection signal is entered, a reset extending circuit which is initialized by the assertion of the power-on reset signal and, after the power-on reset signal is negated, supplies a second signal which takes on a second logical value when an external clock signal is first entered and a third logical value after the lapse of a prescribed length of time determined by counting the external clock signals after the first signal of the first logical value is entered, a detecting circuit which is initialized by the assertion of the power-on reset signal and

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