Power on reset circuit

Details Power on reset circuit Power on reset circuit

2003-04-04

2004-03-23

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06710634

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power on reset circuits, and more particularly, to a power on reset circuit that is incorporated in a semiconductor device and generates a reset signal for resetting the semiconductor device at the time of power on.
2. Description of the Background Art
Conventionally, a semiconductor integrated circuit device (for example, DRAM, SRAM) is provided with a power on reset circuit (hereinafter, referred to as a “POR circuit”) for resetting an internal circuit when an external power supply voltage VDD is turned on.
An output signal POR# of POR circuit remains at an L level until external power supply voltage VDD is raised from 0 V to a prescribed voltage Vres. When external power supply voltage VDD exceeds Vres, output signal POR# attains an H level. Voltage Vres is set lower than a certain range of the power supply voltage with which a product is guaranteed to normally operate. Herein, such a range is called a “guaranteed range”. For example, if a product is designed to operate with 3.3 V (hereinafter, such product is referred to as a “3.3 V product”), the guaranteed range of the power supply voltage is normally from 3.0 V to 3.6 V. Thus, Vres is set approximately at 2.5 V in this case. During a time period in which power supply voltage VDD is not greater than Vres and signal POR# is at an L level, the internal circuitry of the semiconductor integrated circuit device, or more specifically, a redundant circuit of a memory device, a register or state machine of every kind, is initialized.
In the semiconductor integrated circuit device, in association with miniaturization of MOS transistors, the power supply voltage has been downscaled from initial 5 V to 3.3 V or to 2.5 V, further to 1.8 V or to 1.5 V. Consequently, Vres of POR circuit has also been downscaled.
FIG. 9
is a circuit diagram showing a configuration of such POR circuit
30
, which is similar to the one disclosed in U.S. Pat. No. 5,703,510.
Referring to
FIG. 9
, POR circuit
30
includes a P channel MOS transistor
31
, an N channel MOS transistor
32
, capacitors
33
,
34
, and CMOS inverters
35
-
37
. P channel MOS transistor
31
is connected between a line of power supply potential VDD and a node N
1
, and has its gate connected to node N
1
. P channel MOS transistor
31
constitutes a diode element. N channel MOS transistor
32
is connected between node N
1
and a line of ground potential GND, and has its gate connected to a line of power supply potential VDD. N channel MOS transistor
32
constitutes a resistance element of high resistance. Capacitor
33
is connected between node N
1
and a line of ground potential GND.
Inverter
35
includes a P channel MOS transistor
38
and an N channel MOS transistor
39
. P channel MOS transistor
38
is connected between a line of power supply potential VDD and a node N
2
, and has its gate connected to node N
1
. N channel MOS transistor
39
is connected between node N
2
and a line of ground potential GND, and has its gate connected to node N
1
.
Inverter
36
includes a P channel MOS transistor
40
and an N channel MOS transistor
41
. P channel MOS transistor
40
is connected between a line of power supply potential VDD and node N
1
, and its gate is connected to node N
2
. N channel MOS transistor
41
is connected between node N
1
and a line of ground potential GND, and its gate is connected to node N
2
. Inverters
35
and
36
constitute a latch circuit.
Capacitor
34
is connected between a line of power supply potential VDD and node N
2
. Node N
2
is connected to an input node of inverter
37
. An output signal of inverter
37
becomes signal POR#.
Hereinafter, Vres of POR circuit
30
will be described. In this POR circuit
30
, to obtain Vres lower than that would be obtained by the POR circuit disclosed in the above-mentioned U.S. Pat. No. 5,703,510, the diode element (P channel MOS transistor
31
) connected between the line of power supply potential VDD and node N
1
is reduced from the two stages to one stage, and at the same time, the threshold voltage VTC of inverter
35
is reduced to the level of the threshold voltage VTN of N channel MOS transistor
39
.
More specifically, threshold voltage VTC of CMOS inverter
35
is expressed as follows:
VTC
=
 
⁢
VDD
+
VTP
+
VTN
⁢
B
R
1
+
B
R
=
 
⁢
VDD
+
VTP
B
R
+
VTN
1
B
R
+
1
wherein VTP is a threshold voltage of P channel MOS transistor
38
; &bgr;
R
represents a ratio &bgr;
N
/&bgr;
P
between &bgr;
N
of N channel MOS transistor
39
and &bgr;
P
of P channel MOS transistor
38
. &bgr;
N
represents a ratio W
N
/L
N
of a gate width W
N
to a gate length L
N
of N channel MOS transistor
39
, and &bgr;
P
represents a ratio W
P
/L
P
of a gate width W
P
to a gate length L
P
of P channel MOS transistor
38
. Thus, by adjusting &bgr;
N
=W
N
/L
N
and &bgr;
P
=W
P
/L
P
, it is possible to make &bgr;
R
=&bgr;
N
/&bgr;
P
larger than 1, whereby VTC nearly equal to VTN is attained.
If node N
1
is at an L level, P channel MOS transistor
40
of inverter
36
is rendered non-conductive, and N channel MOS transistor
41
is conductive. If &bgr;
N
of N channel MOS transistor
41
is made sufficiently small, potential V
1
of node N
1
becomes approximately equal to VDD−VTP, wherein VTP represents a threshold voltage of P channel MOS transistor
40
.
If potential V
1
of node N
1
exceeds threshold potential VTN of inverter
35
, potential V
1
of node N
1
inverts from an L level to an H level. Thus, power supply voltage VDD at the time when potential V
1
of node N
1
rises from an L level to an H level, i.e., Vres, becomes equal to VTN+VTP.
FIG. 10
shows time charts illustrating the operation of POR circuit
30
shown in FIG.
9
. Referring to
FIG. 10
, at the initial state, node N
1
is at a ground potential GND since it is grounded through a resistance element (N channel MOS transistor
32
) of high resistance. Assume that external power supply potential VDD is switched on at time t
0
and power supply potential VDD rises towards 1.8 V in proportion to time. When potential VDD>VTP, the diode element (N channel MOS transistor
31
) turns on, and potential V
1
of node N
1
becomes equal to VDD−VTP.
At time t
1
, when potential V
1
(=VDD−VTP) of node N
1
exceeds threshold potential VTN of inverter
35
, the output level of inverter
35
inverts from an H level to an L level, and the output level of inverter
36
rises from an L level to an H level, so that potential V
1
of node N
1
rises from VDD−VTP to VDD. Power supply voltage VDD at this time is Vres, and Vres=VTN+VTP in this POR circuit
30
. Therefore, signal POR# is at an L level from time t
0
to time t
1
, and it rises to an H level at time t
1
. Even if power supply voltage VDD fluctuates in a range higher than VTN afterwards, V
1
=VDD, and thus, signal POR# remains at the H level (time t
1
-t
7
). When power supply voltage VDD drops lower than VTN (time t
8
), MOS transistors
31
,
38
,
39
,
40
,
41
are rendered non-conductive. Electric charges stored in capacitor
33
are discharged through the resistance element (N channel MOS transistor
32
) of high resistance, and POR circuit
30
returns to its initial state.
When power supply voltage VDD of a semiconductor integrate circuit device is downscaled, the threshold voltage of a MOS transistor should be reduced correspondingly. In practice, however, to lower power consumption by restricting a leakage current, the threshold voltage of MOS transistor is not downscaled. More specifically, the threshold voltage of MOS transistor, which was 0.8 V for 5 V and 3 V products, is maintained at 0.8 V even for 1.8 V and 1.5 V products. Thus, Vres of the POR circuit
30
shown in
FIG. 9
becomes equal to VTN+VTP=0.8+0.8=1.6 V.
The guaranteed range of the power supply voltage for a 1.8 V product is 1.62 V to 1.98 V. Thus, the margin guaranteed by Vres=1.6 V as

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