Power-on-reset circuit

Details Power-on-reset circuit Power-on-reset circuit

1992-12-28

1994-04-05

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 323315, 330288, G05F 326

Patent

active

053008227

ABSTRACT:
A power-on-reset circuit includes a plurality of MOS transistors and a first depletion type N-channel MOS transistor connected in series to an input terminal of a current mirror circuit. A capacitor is connected between the input terminal and a voltage supply terminal. A second depletion type N-channel MOS transistor having a low current driving capacity is connected to an output terminal of the current mirror circuit. The degree of integration can be increased by constituting an integrating circuit with depletion type N-channel MOS transistors in place of a resistor. In addition, the voltage supply voltage is compared to the sum of the threshold voltage of the plurality of MOS transistors. This makes it possible to initialize the internal circuit positively even if the rise time of the voltage supply voltage becomes larger than the time constant of the integrating circuit.

REFERENCES:
patent: 4591739 (1986-05-01), Nagano
patent: 4767942 (1988-08-01), Minami et al.
patent: 4994729 (1991-02-01), Taylor
patent: 5047706 (1991-09-01), Ishibashi et al.
patent: 5057792 (1991-10-01), Gay

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