Power-on reset circuit

Details Power-on reset circuit Power-on reset circuit

2002-01-08

2002-10-22

Vu, Bao Q. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

Reexamination Certificate

active

06469477

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power-on reset circuit set in a semiconductor integrated circuit and generating a one-shot power-on reset pulse (one-shot pulse) in the power application to reset other circuits in the semiconductor integrated circuit.
2. Related Art
A conventional power-on reset circuit has a capacitor charge time constant circuit configured by a charge capacitor, and resistance or current generator, and generates a one-shot pulse in the power application. However, there is a problem in the power-on reset circuit having only the capacitor charge time constant circuit that the one-shot pulse is not generated when the ramp-up speed of a power supply voltage is slower than that of capacitor charge time constant. There are descriptions of arts. coping with this problem such as the ones disclosed in the following documents.
Document 1: JP, 63-246919, A
Document 2: JP, 4-72912, A
Document 3: JP, 6-196989, A
Document 4: U.S. Pat. No. 5,930,129
The power-on reset circuit disclosed in the document 1 comprises a flip-flop set in response to a power supply voltage application and a power supply voltage detection circuit resetting the flip-flop forcibly after a prescribed delay from the time of the power supply voltage rising over a prescribed potential.
The power-on reset circuit disclosed in the document 2 comprises a power supply voltage detection circuit detecting the rise of power supply voltage to a prescribed voltage, a delay circuit delaying the output signal of the power supply voltage detection circuit and a waveform shaping circuit achieving a waveform shaping of the output signal of the delay circuit.
The power-on reset circuit disclosed in the document 3 comprises a voltage control means outputting the output voltage, at which the power supply voltage is set, in the output voltage less than a predetermined voltage and a pulse output circuit outputting a prescribed pulse in response to the difference between the input voltage of the voltage control means and a predetermined voltage reaching a prescribed value after inputting the output voltage of the voltage control means.
The power-on reset circuit disclosed in the document 4 comprises: a voltage sensing means; an electric current path disconnecting means; a capacitor charge time constant circuit having a power supply voltage sensing circuit sensing the power supply voltage application when the electric current disconnecting means is turned on, an electric current flowing path means flowing path based on the sensed voltage, a capacitor charging based on the time constant through the electric current flowing path means, and a discharging means; and an output circuit.
However, when the conventional power-on reset circuit is configured by using a minute MOS element in which the off-leakage current through the MOS (under high temperature) tends to increase with recent development of process-minuteness of the semiconductor integrated circuit, there are following problems therein.
FIGS. 24-27
are circuit diagrams showing examples of the conventional power-on reset circuit, and are respectively shown in the documents 1-4.
The power-on reset circuit disclosed in the document 1 comprises a flip-flop
2
configured by two inverters
2
a
and
2
b
and detecting and keeping the rise of power supply voltage, a capacitor
3
connected to the flip-flop
2
, a MOS transistor
4
and a power supply voltage circuit
10
. The power supply voltage circuit
10
has two steps of inverters
11
and
12
, a MOS diode array
14
configured by plural MOS diodes
13
, a capacitor
15
and a MOS transistor
16
, the connection of which is shown in FIG.
24
.
As described above, the power-on reset circuit disclosed in the document
1
has the configuration that a reset signal for the flip-flop
2
is forcibly generated by establishing a supportive circuit in parallel to a general power-on reset circuit comprising a capacitor, a resistance (MOS diode array) and an inverter. When the off-leakage current is sent on the MOS diode array in the circuit configuration, the charge of the capacitor
15
is started by the off-leakage current through the MOS diode array and a forcible reset signal for the flip-flop
2
is generated at the moment of the power application, at the ramp-up period of the power supply voltage in the power application, before the power supply voltage reaches the threshold voltage at the MOS diode array. As a result, a one-shot pulse (power-on reset signal) cannot be accurately generated.
The power-on reset circuit disclosed in the document 2 is configured by a power supply voltage detection circuit
20
, a delay circuit
30
and a waveform shaping circuit
40
as shown in FIG.
25
. The power supply voltage detection circuit
20
has a resistance
21
and an N-channel type MOS diode
22
which are connected between a power supply potential Vcc and a ground, and has a resistance
24
one end of which is connected to a connection point N
1
of the resistance
21
and the MOS diode
22
. An inverter
25
operating with the power supply voltage and the drain of an N-channel type MOS transistor (hereafter, referred to as NMOS)
26
are connected to a connection point N
2
of resistances
23
and
24
. The inverter
25
is configured by a P-channel type MOS transistor (hereafter, referred to as PMOS)
25
a
and NMOS
25
b
. The gate of the NMOS
26
is connected to the output terminal of the inverter
25
while the source of the NMOS
26
is connected to the ground. The delay circuit
30
has NMOS
31
the source of which is connected to the output terminal of the inverter
25
and the gate of which is connected to the power supply potential Vcc, and has a capacitor
32
connected between the drain of the NMOS
31
and the ground. The waveform shaping circuit
40
has an inverter
41
the input terminal of which is connected to a connection point N
3
of the NMOS
31
and the capacitor
32
, and has PMOS
42
the gate of which is connected to the output terminal of the inverter
41
.
As described above, the power-on reset circuit disclosed in the document 2 has the configuration that the resistances
21
,
23
and
24
in the power supply voltage detection circuit
20
divide the voltage between the power supply potential Vcc and the ground. Therefore, there is a problem that since current flows through the resistances
21
,
23
and
24
, the current consumption cannot reach
0
even after an one-shot pulse is generated.
Further, when the off-leakage current is sent on the PMOS
42
in the waveform shaping circuit
40
the charge of the capacitor
32
is started by the off-leakage current through the PMOS
42
and the PMOS
42
is forced to be turned on by inverting the output of the inverter
41
and NMOS
26
in the power supply voltage detection circuit
20
is also forced to be turned on, at the ramp-up period of the power supply voltage in the power application, before the power supply voltage reaches the prescribed power supply voltage detected at the power supply voltage detection circuit
20
. As a result, the one-shot pulse (power-on reset signal) cannot be accurately generated.
The power-on reset circuit disclosed in the document 3 has an enhancement-type PMOS
51
the source of which is connected to a power supply potential Vdd and has a voltage control circuit
52
connected between the drain of the PMOS
51
and the ground thereof, as shown in FIG.
26
. The voltage control circuit
52
has a depression-type NMOS
52
a
the drain of which is connected to the source of the PMOS
51
, and has an enhancement-type NMOS
52
b
the gate and drain of which are connected to the gate and source of the NMOS
52
a
. The source of the NMOS
52
b
is connected to the ground. The drain of an enhancement-type NMOS
54
and a pulse generation part
53
are connected to the output terminal of the voltage control circuit
52
. The source of the enhancement-type NMOS
54
is grounded. The pulse generation part
53
has an enhancement-type PMOS
53
a
the source of which is c

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