Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-08-22
2002-04-23
Cunningham, Terry (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S539000, C323S313000, C323S315000
Reexamination Certificate
active
06377090
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a circuit for resetting when a supply voltage appears, generally called “Power-On-Reset” circuit or “POR” circuit in the Anglo-Saxon terminology.
2. Description of the Related Art
When powered on, most of the programmed or programmable type logic circuits, in particular microprocessors, must be set in a zero state or RESET state in order to assure that their constitutive elements do not present undetermined logic states. The POR circuits, provided for this, deliver RESET signal when the supply voltage rises and reaches a first switching threshold V
th1
, and release the RESET signal when the voltage reaches a second switching threshold V
th2
. According to the chosen convention, the active value of the RESET signal may be 1 or 0. The release of the RESET signal corresponds to its setting to 0 in the first case and to its setting to 1 in the second case.
A difficulty in the design of a POR circuit, in particular in CMOS technology, is to obtain a release threshold V
th2
of the RESET signal which is constant and little sensitive to the sizes of the MOS transistors, in particular the ratio W/L between the width W and the length L of the gate of the transistors. This ratio is indeed likely to vary unintentionally, from a circuit to another, because of tolerances of the manufacturing method.
Another difficulty is to obtain a release threshold V
th2
of the RESET signal which is little sensitive to the temperature of the circuit.
FIG. 1
shows the electrical diagram of a conventional circuit POR1 supplied by a voltage V
DD
. In this diagram, the references of the PMOS transistors begin with a letter “P” and the references of the NMOS transistors begin with a letter “N”. The NMOS transistors have a threshold voltage V
TN
and the PMOS transistors have a threshold voltage V
TP
.
The circuit POR
1
comprises a polarisation stage comprising, arranged in series, a ballast transistor PM
1
(comparable to a resistance) and a diode transistor NM
2
, transistor PM
1
having its gate connected to ground and transistor NM
2
having its gate fed back to its drain. The mid-point of the transistors PM
1
, NM
2
delivers a voltage V
1
applied to the gates of two other transistors PM
3
, NM
4
arranged in series, forming a switching stage. The mid-point of transistors PM
3
, NM
4
delivers an output voltage V
2
of the circuit POR
1
. The active state of the RESET signal being here by convention a logical “1”, the output voltage V
2
is applied to the input of an inverting gate INV
1
formed by two other transistors PM
5
, NM
6
, whose output delivers the RESET signal.
When the voltage V
DD
appears, the voltage V
1
copies the voltage V
DD
as long as the diode transistor NM
2
is OFF. The first switching threshold V
th1
is reached when the voltage V
DD
becomes equal to the threshold voltage V
TN
. The diode transistor NM
2
and the transistor NM
4
turn ON, the voltage V
2
passes to 0 (ground GND) and the RESET signal passes to 1.
The second switching threshold V
th2
, or release threshold of the RESET signal, is reached by the voltage V
DD
when the source-gate voltage V
SG
of transistor PM
3
becomes equal to its threshold voltage V
TP
, the transistor PM
3
turning ON. The voltage V1 at the terminals of the diode transistor NM
2
being at this moment equal to:
V
1
=V
TN
+ri
(1)
r being the series resistance of transistor NM
2
and i the current passing through it, the switching threshold V
th2
is thus equal to:
V
DD
=V
th2
=V
TP
+V
1
=V
TP
+V
TN
+ri
(2)
In practice, the threshold voltages V
TN
and V
TP
are in the order of 0.8 V, and the voltage ri is in the order of 0.6 V. The switching threshold V
th1
is thus in the order of 0.8 V and the switching threshold V
th2
is in the order of 2,2 V at ambient temperature. As it can be seen in
FIG. 2
, the voltage of 0.8 V corresponds to a logic “1” of the RESET signal at a moment when this signal is set to 1 and the voltage of 2,2 V corresponds to a logic “1” of the RESET signal at a moment when it is brought back to 0 by the turning ON of transistor PM
3
.
The relation (2) shows that the switching threshold V
th2
depends on the threshold voltages V
TN
and V
TP
, as well as on the resistance r of the diode transistor NM
2
and the current i flowing through the polarization stage. However, the threshold voltages V
TP
or V
TN
of MOS transistors are sensitive to temperature and increase when temperature decreases. Also, the resistance r of diode transistor NM
2
depends on the ratio W/L of the gate of transistor NM
2
and the current i depends on the ratio W/L of the gate of the ballast transistor PM
1
, which determines the electric resistance of this transistor.
The switching threshold V
th2
is thus sensitive to the ratio W/L of the gates of the switching stage transistors and to the temperature of the circuit.
The present invention is directed to overcome this drawback.
SUMMARY OF THE INVENTION
More particularly, a first object of the present invention is to provide a POR circuit which presents a switching threshold V
th2
not much sensitive to the ratio W/L of the gates of the MOS transistors.
A second object of the present invention is to provide a POR circuit which presents a switching threshold V
th2
not much sensitive to variations of temperature.
The foregoing objects are achieved as is now described. To that effect, the present invention provides a circuit for delivering a logic signal at the appearance of a supply voltage, comprising means for connecting an output node of the circuit to ground when the supply voltage reaches a first switching threshold, and means for connecting the output node to the supply voltage when the supply voltage reaches a second switching threshold, wherein the means for connecting the output node to the supply voltage comprise a switching transistor whose gate is polarized by a reference voltage taken at the terminals of a first precision resistance traversed by a current delivered by a current generator.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4978905 (1990-12-01), Hoff et al.
patent: 5103115 (1992-04-01), Ueda et al.
patent: 5302861 (1994-04-01), Jelinek
patent: 5774013 (1998-06-01), Groe
patent: 5852376 (1998-12-01), Kraus
patent: 5929672 (1999-07-01), Mitani
patent: 5936443 (1999-08-01), Yasuda et al.
patent: 6137324 (2000-10-01), Chung
patent: 2 757 713 (1996-12-01), None
Cunningham Terry
Englund Terry L.
STMicroelectronics S.A.
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