Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-06-23
2001-12-11
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06329852
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power on reset circuit and more particularly, to a power on reset circuit capable of obtaining a stable operation regardless of a ramp up time of a power supply voltage or a process variation.
2. Description of the Prior Art
A flash EEPROM generally includes logic circuits, and after a setup of a power supply voltage, the logic circuits should be initialized with a predetermined state. Thus, a power on reset circuit is used to generate a signal capable of initializing the logic circuits as soon as the power supply voltage is set up.
Hereinafter, a conventional power on reset circuit will be described with reference to FIG.
1
.
FIG. 1
is a circuit diagram showing a conventional power on reset circuit, and the construction thereof is as follows.
First to third PMOS transistors P
1
to P
3
are coupled between a power terminal and a second node Q
2
. The first PMOS transistor P
1
is driven according to a potential of a first node Q
1
, the second PMOS transistor P
2
serves as a diode, and the third PMOS transistor P
3
, whose a gate terminal is coupled to a ground terminal Vss, is maintained at a turned-on state. First to fifth NMOS transistors N
1
to N
5
are coupled between the second node Q
2
and the ground terminal Vss and are always maintained at a turned-on state since their gate terminals are coupled to the power terminal. A sixth NMOS transistor N
6
is coupled between the power terminal and the second node Q
2
, whose a gate terminal is coupled to the second node Q
2
. Fourth and fifth PMOS transistors P
4
and P
5
are coupled between the power terminal and a third node Q
3
. The fourth PMOS transistor P
4
is driven according to a potential of the first node Q
1
, and the fifth PMOS transistor P
5
, whose a gate terminal is coupled to the ground terminal Vss, is always maintained at a turned-on state. Seventh to ninth NMOS transistors N
7
to N
9
are coupled between the third node Q
3
and the ground terminal Vss, whose gate terminals are coupled to the second node Q
2
, respectively. Third and fourth capacitors C
3
and C
4
are coupled in parallel between the power terminal and the third node Q
3
. Tenth to thirteen NMOS transistors N
10
to N
13
are coupled between the third node Q
3
and the ground terminal Vss, whose gate terminals are coupled to the first node Q
1
, respectively. A signal of the third node Q
3
is delayed through first to sixth inverters I
1
to I
6
to output a reset signal RST. Meanwhile, a plurality of serially-coupled PMOS transistors and a fourteenth NMOS transistor N
14
are coupled between the power terminal and the first node Q
1
. Each gate terminal of the serially-coupled PMOS transistors is coupled to the ground terminal Vss. A first capacitor C
1
is coupled between the first node Q
1
and the ground terminal Vss.
Hereinafter, a driving method of the conventional power on reset circuit will be described.
At an initial state, the first node Q
1
is maintained at a low state. Therefore, if the power supply voltage Vcc is applied more than a threshold voltage Vpn of a PMOS transistor, the first and fourth PMOS transistors P
1
and P
4
are turned on. The power supply voltage Vcc is supplied to the second node Q
2
through the turned-on first PMOS transistor P
1
, the second and third PMOS transistors P
2
and P
3
. However, the second node Q
2
is maintained at a low state through the first to fifth NMOS transistors N
1
to N
5
, coupled between the second node Q
2
and the ground terminal Vss, whose gate terminals are coupled to the power supply terminal. Since the second node Q
2
is maintained at a low state, the sixth NMOS transistor N
6
is turned on, so that the power supply voltage Vcc is supplied to the second node Q
2
through the sixth NMOS transistor N
6
. The voltage Vcc is discharged to the ground terminal Vss through the second capacitor C
2
so that the second node Q
2
is dropped to the ground level. Accordingly, the sixth to ninth NMOS transistors N
7
to N
9
are turned off, wherein the sixth to ninth NMOS transistors N
7
to N
9
are coupled between the third node Q
3
and the ground terminal Vss, whose gate terminals are coupled to the second node Q
2
. Meanwhile, the power supply voltage Vcc is supplied to the second node Q
2
through the turned-on fourth PMOS transistor P
4
and the fifth PMOS transistor P
5
. Since the seventh to ninth PMOS transistors N
7
to N
9
are turned off, the second node Q
2
is maintained at a high state. Since the tenth to thirteenth NMOS transistors N
1
O to N
13
coupled between the third node Q
3
and the ground terminal Vss, whose gate terminals is coupled to the third node Q
3
, are turned off by a potential of the first node Q
1
having the low state, the third node Q
3
is maintained at a high state. A signal of the third node Q
3
maintained at the high state is delayed through the first to sixth inverters I
1
to I
6
for a predetermined time to output a reset signal RST, thereby resetting a chip.
The gradually-increasing power supply voltage Vcc is delayed due to a plurality of the serially-coupled PMOS transistors and the first capacitor C
1
for a predetermined time and supplied to the first node Q
1
, and a potential of the first node Q
1
is increased due to the voltage. The first and the fourth PMOS transistors P
1
and P
4
are turned off, so that a supply of the power supply voltage is stopped. The tenth to the thirteenth NMOS transistors N
1
O to N
13
are turned off, so that a potential of the third node Q
3
becomes a low state. As a result, since a signal of the low state is outputted through the first to sixth inverters I
1
to I
6
, a reset operation is stopped.
FIGS. 2 and 3
shows the output waveforms of
FIG. 1
according to a ramp up time. Here,
FIG. 2
is an output waveform when the ramp up time is 5 msec, and
FIG. 3
is an output waveform when the ramp up time is 200 msec.
As can be seen from
FIG. 2
, the power up reset circuit such as shown in
FIG. 1
generates the reset signal of approximately 2V for 2msec, when the power supply voltage Vcc is applied and increased. As can be seen from
FIG. 3
, however, the reset voltage is not generated when the ramp up time is 200 msec. That is, in a slow ramping of 200 msec as an optimized parameter, since the reset signal is not generated, the chip can not be reset.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a power on reset circuit capable of generating a reset signal regardless of a ramp up time of a power supply voltage.
To achieve the above object, the power on reset circuit in accordance with the present invention comprises a first means for controlling a potential of a first node to a first potential according to a potential of a second node, a second means for supplying the power supply voltage to be ramped up to the second node according to the potential of the first node, a third means for determining a potential of a third node by inverting and delaying the potential of the second node, a fourth means for controlling a potential of a fourth node to a second potential according to the potential of the third node, a fifth means for inverting and delaying the potential of the fourth node, a sixth means for outputting the potential of the third node to an output terminal according to an output signal from said fifth means and its inverted signal, and a seventh means for controlling a signal of the output terminal according to the inverted signal of the output signal from said fifth means.
REFERENCES:
patent: 3895239 (1975-07-01), Alaspa
patent: 4797584 (1989-01-01), Aguti et al.
patent: 5111067 (1992-05-01), Wong et al.
patent: 5115146 (1992-05-01), McClure
patent: 5151614 (1992-09-01), Yamazaki et al.
patent: 5448528 (1995-09-01), Nagai
patent: 5511034 (1996-04-01), Hirata
patent: 5552725 (1996-09-01), Ray et al.
patent: 5555166 (1996-09-01), Sher
patent: 5631867 (1997-05-01), Akamatsu et al.
patent: 5682111 (1997-10-01), Bacrania et al.
patent: 5696461 (1997-12-01
Callahan Timothy P.
Hyundai Electronics Industries Co., Inc.
Nguyen Hai L.
Pennie & Edmonds LLP
LandOfFree
Power on reset circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power on reset circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power on reset circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2570236