Power on reset circuit

Details Power on reset circuit Power on reset circuit

1998-06-12

2000-07-04

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

H03K 1722

Patent

active

060844469

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to power on reset circuitry. More specifically, the present invention provides a power on reset circuit which is operable with low leakage current and high reliability.
2. Description of Related Art
Power on reset circuits are used in integrated circuits to generate a reset signal, when the power supply voltage reaches an operating level. For example, in U.S. Pat. No. 5,345,424, a power on reset circuit is illustrated in FIG. 3. One disadvantage of the circuit described in U.S. Pat. No. 5,345,424arises because of DC leakage current occurs through the circuit when the power is on. As low power integrated circuits are becoming more important, this DC leakage is unacceptable.
One alternative approach used in prior art integrated circuits is illustrated in FIG. 1. The circuit includes an input driver composed of transistors M1-M5. This input driver drives a voltage at node 1 on the input of an inverter formed by transistors M7 and M8. A clamp transistor M6 is connected between the input of the inverter and the supply potential. A capacitor formed by transistor M9 is connected between the supply potential and the output of the inverter formed by transistors M7 and M8. The capacitor connected transistor M9 serves to couple the output of the inverter to the level of the supply potential, until the voltage at the input of the inverter reaches the trigger point of transistor M8. When M8 turns on, the capacitor is discharged to ground. Thus, during a power up sequence, the output of the inverter is pulled up as the supply potential increases. After the voltage at node 1 reaches the turn on potential of transistor M8, the pulse being formed by the pull up of node 2 is ended. That pulse is translated by the buffer composed of the two invertors in series into a power on reset signal. Transistor M6 serves to clamp the input of the inverter formed by transistors M7 and M8 to a level near the supply potential during a power down sequence. Thus, node 1 cannot increase more than the threshold of transistor M6 above the supply potential when the supply potential approaches ground. In this way, node 1 is low enough during a subsequent power up sequence to ensure that the inverter has an input below the trip point of transistor M8, allowing the capacitive coupling across transistor M9 to work in the formation of the power on pulse. This circuit however suffers the disadvantage that the input of the inverter (labeled node 1) is not driven to the level of the supply potential during normal operation of the circuit. This causes leakage current through transistor M7, which is unacceptable for low power devices.
Another disadvantage of the circuit of FIG. 1 occurs because the power down level may not reach all the way to ground. If the final power down level is about 0.5 volts, and the threshold of the clamp transistor M6 is about 0.8 volts, then it is possible that node 1 will be higher than the trip point of transistor M8 when the next power up sequence occurs. Under these conditions, transistor M8 discharges the capacitor at the output of the inverter while the supply potential is ramping up. No power on pulse is generated in this case.
FIG. 2 illustrates an improved circuit, also used in the prior art. According to the embodiment of FIG. 2, an additional low threshold transistor M10 is connected between the input of the inverter formed by transistors M7 and M8 and ground. The low threshold transistor M10 ensures that the voltage on the input of the inverter is pulled down to about 0.6 volts, that is the threshold of transistor M10, which is lower than the threshold of transistor M8 during the power down condition. This ensures that the circuit will operate during a power down condition in which the supply potential does not fall all the way to ground. However, the circuit of FIG. 2 still suffers the disadvantage that the potential at node 1 on the input of the inverter formed by transistors M7 and M8 does not reach the supply potential during n

REFERENCES:
patent: 5345424 (1994-09-01), Landgraf
patent: 5528182 (1996-06-01), Yokosawa
patent: 5638330 (1997-06-01), Confalonieri et al.
patent: 5646902 (1997-07-01), Park
patent: 5734281 (1998-03-01), Morishawa et al.

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