Power-on reset circuit

Details Power-on reset circuit Power-on reset circuit

1981-07-20

1983-10-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072383, 307246, 307585, 307296R, 377107, H03K 1722, H03K 17284, H03K 17687

Patent

active

044095015

ABSTRACT:
A power-on reset circuit in which a first CMOS inverter drives a second CMOS inverter to turn on a third and fourth CMOS inverter. A reset pulse results at the output of the fourth inverter while the third inverter holds a first MOSFET in an off condition and a capacitor is charged through a resistive network comprised of two MOSFETs. When the capacitor is charged past the switching point of the first inverter, the POR pulse is terminated and the first MOSFET is turned on, allowing the capacitor to be charged to the point that no static current flows through the reset circuit because no static current flows through the first inverter.

REFERENCES:
patent: 3775693 (1973-11-01), Proebsting
patent: 3895239 (1975-07-01), Alaspa
patent: 3950654 (1976-04-01), Broedner et al.
patent: 4001609 (1977-01-01), Sickert
patent: 4045688 (1977-08-01), Stewart
patent: 4103187 (1978-07-01), Imamura
patent: 4103190 (1978-07-01), Beutler
patent: 4135102 (1979-01-01), Green et al.
patent: 4365174 (1982-12-01), Kucharewski

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