Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-11-07
2003-04-22
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S100000, C345S204000
Reexamination Certificate
active
06552709
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display driving method and a display driving circuit and more particularly to the display driving method and the display driving circuit for a display such as a liquid crystal panel and an electroluminescence panel (EL panel).
The present application claims the Convention Priority of Japanese Patent Application No. Hei11-316872 filed on Nov. 8, 1999 Hei11-316872 filed on Nov. 8, 1999, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 7
is a block diagram showing an electric configuration example of a conventional liquid crystal panel
1
and a display driving circuit disclosed in Japanese Patent Application Laid-open No. Hei11-143432.
The liquid crystal panel
1
is an active matrix driving liquid crystal panel using a thin film transistor (TFT) used as a switch element. Intersection points of n-pieces (n is a positive integer) of scanning electrode
2
1
to scanning electrode
2
n
(gate line) provided at predetermined intervals in a row direction and m-pieces (m is a positive integer) of data electrode
3
1
to data electrode
3
m
(source line) provided at predetermined intervals in a column direction are used as pixels. For each pixel, a liquid crystal cell
4
which is an equivalent capacitive load, a TFT
5
for driving a corresponding liquid crystal cell
4
and a capacitor
6
for storing data charges for one vertical synchronous period are arranged. A data red signal, a data green signal and a data blue signal generated based on a red data D
R
, a green data D
G
and a blue data D
B
to be digital image data are sequentially applied to data electrode
3
1
to data electrode
3
m
and scanning signals are sequentially applied to scanning electrode
2
1
to scanning electrode
2
n
, and thereby a character, an image or a like are displayed.
Further, the conventional display driving circuit of this example is a semiconductor integrated circuit of a CMOS (Complementary Metal Oxide Semiconductor) configuration mainly including a controller
7
, a data electrode driving circuit
8
and a scanning electrode driving circuit
9
.
The controller
7
generates a start pulse SP
1
and a shift clock CK
1
to be supplied to the data electrode driving circuit
8
and a start pulse SP
2
, a shift clock CK
2
and an enable signal EN to be supplied to the scanning electrode driving circuit
9
.
The data electrode driving circuit
8
is mainly provided with a shift register, a data register, a latch, a level shifter, a digital analog converter (DAC) and plural drivers (not shown).
The data electrode driving circuit
8
starts to take red data D
R
, green data D
G
, and blue data D
B
synchronously with the shift clock CK
1
into the shift register based on the start pulse SP
1
, and then, takes output data from the shift register into the data register at a rising of the shift clock CK
1
. Then, the data electrode driving circuit
8
holds the output data temporarily in the latch, converts it into a predetermined voltage by the level shifter, converts the predetermined voltage into analog data red signal, analog data green signal and analog data blue signal by the DAC, applies amplification and buffer to these signals and sequentially applies them to a corresponding data electrode among data electrode
3
1
to data electrode
3
m
in the crystal panel
1
by the plural drivers.
The scanning electrode driving circuit
9
, as shown in
FIG. 8
, is mainly provided with a shift register
10
, NAND gate
11
1
to NAND gate
11
n
and driver
12
1
to driver
12
n
.
The shift register
10
is a serial-in parallel-out shift register including n-pieces of delay flip-flops (DFFS), executes a shift operation for shifting the start pulse SP
2
synchronously with the shift clock CK
2
based on a power supply voltage V
CC
and supplies each bit of n-bits of parallel data to each second input terminal of NAND gate
11
1
to NAND gate
11
n
. Each of NAND gate
11
1
to the NAND gate
11
n
inverts each bit of n-bits parallel data and supplies an inverted bit to a corresponding driver among driver
12
1
to driver
12
n
when each enable signal EN supplied from the controller
7
to each first input terminal is an “H” level. Each driver
12
1
to the driver
12
n
applies amplification and buffer to each bit of n-bits of parallel data inverted and supplied from a corresponding NAND gate (NAND gate
11
1
to NAND gate
11
n
) and sequentially applies it to a corresponding scanning electrode among scanning electrode
2
1
to scanning electrode
2
n
as n-pieces of scanning signals in the liquid crystal panel
1
.
Next, explanations will be given of a part of an operation in the display driving circuit of the above-mentioned configuration. First, when a power supply is turned ON, the power supply voltage V
CC
is applied to the shift register
10
in the scanning electrode driving circuit
9
.
In this case, in order to avoid latch-up in the scanning electrode driving circuit
9
, the controller
7
applies a power-on-reset (not shown) so as to not output various control pulses until a constant time in which the power supply voltage V
CC
becomes stable passes after the power supply is turned ON.
Here, the latch-up is a phenomenon in which an electric current continuously flows from a power supply terminal to a ground terminal so long as the power supply voltage is lowered in a semiconductor integrated circuit of a CMOS configuration. Explanations will be given of reasons that the latch-up occurs in the scanning electrode driving circuit
9
. Immediately after turning the power supply ON, output data from the shift register is irregular. When such irregular output data are directly supplied to driver
12
1
to driver
12
n
, in a worst case, namely, in a case in that all output data of the shift register
10
are different, an irregular over-current exceeding current supply capacities of driver
12
1
to driver
12
n
which is a current of several times of a capacity in a normal operation flows into all driver
12
1
to the driver
12
n
and a large voltage drop occurs, therefore, the latch-up occurs.
Then, after the constant time passes and power-on-reset is released, the controller
7
supplies the start pulse SP
2
of one vertical synchronous period and the shift clock CK
2
of one horizontal synchronous period to the shift register
10
and supplies an enable signal EN of an “L” level to each first input terminal of NAND gate
11
1
to NAND gate
11
n
. With this operation, the shift register
10
starts a normal shift operation, however, the enable signal is the “L” level, therefore, regardless of any state of each bit of n-bits of parallel data output NAND gate
11
1
to NAND gate
11
n
is kept at the “H” level.
Then, the shift register
10
starts the normal shift operation, after at least one vertical synchronous period in a display area of the liquid crystal display
1
passes, the controller
7
sets the enable signal EN to the “H” level. With this operation, it becomes possible for NAND gate
11
1
to NAND gate
11
n
to invert and output each bit of n-bits of parallel data supplied from the shift resister
10
. Therefore, when a next start pulse SP
2
is supplied from the controller
7
, driver
12
1
to driver
12
n
apply amplification and buffer to each bit of n-bits of parallel data inverted and supplied from a corresponding NAND gate among NAND gate
11
1
to NAND gate
11
n
and sequentially apply to a corresponding scanning electrode among scanning electrode
2
1
to scanning electrode
2
n
in the liquid crystal panel
1
as n-pieces of scanning signals.
As above described, with this configuration of the example, output data of the shift register
10
are not transferred to each driver
12
1
to driver
12
n
until all irregular output data of the shift register
10
are erased immediately after releasing the power-on-reset of the controller
7
. As a result, it is possible for driver
12
1
to driver
12
n
to prevent an irregular over-current from occurring and
Lao Lun-Yi
NEC Corporation
Scully Scott Murphy & Presser
Sheng Tom V.
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