Power-off protection device

Details Power-off protection device Power-off protection device

2002-01-30

2003-07-01

Vu, Bao Q. (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

C361S078000

Reexamination Certificate

active

06587324

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a power-off protection device. In particular, the present invention relates to a power-off protection device to prevent abnormal high-level signal generated during main power shutdown.
2. Description of the Related Art
Recently, most PC products and peripheral devices have adopted switching power, which uses pulse-width modulation (PWM) to control integrated circuits (IC) to act as the power controlling circuit.
FIG. 1
depicts a circuit diagram of a conventional power supply. Pulse-width modulation integrated circuit
10
(PWM IC) outputs a voltage control signal responding to the voltage modulating signal at the input of the PWM IC
10
provided by the CPU
12
. The voltage control signal is a high frequency signal. The pulse width of the voltage control signal is adjusted responding to the voltage modulating signal provided by the CPU
12
. Then, the voltage control signal is input into a voltage generating circuit
14
. The voltage generating circuit
14
generates operating voltage V
op
from the power provided by V
cc2
according to the voltage control signal, then the operating voltage V
op
is provided to the CPU
12
for operation.
FIG. 2
shows a table of the signals output from CPU
12
(VID
0
~VID
4
) to the PWM IC
10
and the output voltages V
op
of the voltage generating circuit
14
. The output voltage V
op
of the power supply is controlled by the signals input to the PWM IC
10
. In
FIG. 1
, the inputs of the PWM IC
10
(VID
0
~VID
4
) are connected to V
cc1
(3.3V) through pull-up resistor R
1
. Therefore, when the system is not active, the operating voltage V
op
is off while the inputs of the PWM IC
10
(VID
0
~VID
4
) all receive high level signals. In addition, when CPU
10
operates, the PWM IC
10
controls the voltage generating circuit
14
to generate the desired voltage responding to the signals input to the inputs of the PWM IC
10
(VID
0
~VID
4
) from CPU
12
.
Generally, when the main power is turned off, V
cc2
drops to low level faster than V
cc1
, so the system is turned off successfully. However, when an abrupt V
cc1
drop to low level is faster than V
cc2
, at this time, V
cc2
is still at high level, the operating voltage V
op
reaches 1.85V (refer to the table in FIG.
2
), because the inputs of the PWM IC
10
(VID
0
~VID
4
) all receive low level signals when V
cc2
is still at high level, the voltage generating circuit
14
generates the signal at 1.85V from V
cc2
, which damages the CPU.
SUMMARY OF THE INVENTION
The present invention provides a power-off protection device, which adds a reference-voltage maintenance device at the input of the PWM IC to delay the PWM IC power dropping to low level, ensuring that the power of the voltage generating circuit drops to low level first. Thus, the situation in the prior art wherein the inputs of the PWM IC receive low level signals and generate excessive high voltage is prevented.
To achieve the above-mentioned object, the present invention provides a power-off protection device for outputting operating power according to a first level signal and a second level signal, which comprises a processor, a modulating circuit, a power generating circuit, and a reference-voltage maintenance device. The processor outputs a voltage modulating signal. The modulating circuit is coupled to the processor and the first level signal to output a voltage control signal responding to the voltage modulating signal. The power generating circuit is coupled to the second level signal and the modulating circuit to generate the operating power from the second level signal according to the voltage control signal. The reference -voltage maintenance device is coupled to the first level signal and the modulating circuit to delay the drop time of the first level signal to confirm that the first level signal is higher than the second level signal when the first level signal and the second level signal are turned off.


REFERENCES:
patent: 5177408 (1993-01-01), Marques
patent: 6418002 (2002-07-01), Yang et al.
patent: 6449177 (2002-09-01), Chen

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