Power off-loading circuit and method for dissipating power

Details Power off-loading circuit and method for dissipating power Power off-loading circuit and method for dissipating power

1995-10-30

1997-05-20

Hecker, Stuart N.

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

257724, G05F 140

Patent

active

056315481

ABSTRACT:
A power off-loading circuit (10) includes an IC device (11) and a discrete resistor (21), which provide a regulated voltage at an output pin (19) of the IC device (11). The IC device (11) includes a first FET (12), a second FET (14), and an operational amplifier (16). For a low voltage at an input pin (13) of the IC device (11), the first FET (12) conducts a current to a load (25) connected to the output pin (19). For a high voltage at the input pin (13), a large portion of the current is directed through the discrete resistor (21) and the second FET (14). A large portion of power is off-loaded from the IC device (11) and dissipated in the discrete resistor (21) thereby permitting the use of surface mount techniques.

REFERENCES:
patent: 3919601 (1975-11-01), Suko et al.
patent: 4599555 (1986-07-01), Damiano et al.
patent: 4740741 (1988-04-01), Andres et al.
patent: 5029322 (1991-07-01), Einzinger et al.
patent: 5272392 (1993-12-01), Wong et al.
patent: 5408141 (1995-04-01), Devore et al.
patent: 5428682 (1995-06-01), Apfel

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