Power multiplication circuit which reduces an offset voltage of

Details Power multiplication circuit which reduces an offset voltage of Power multiplication circuit which reduces an offset voltage of

1993-07-30

1995-08-01

Nguyen, Vinh

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Plural inputs

324117H, 324117R, G01R 2100

Patent

active

054382580

ABSTRACT:
A power multiplication circuit including a Hall element for generating between voltage output terminals thereof a first output voltage corresponding to a power of a system under measurement. The circuit further includes a voltage polarity detection circuit for detecting a polarity of a power source voltage of the system and an operating circuit connected to receive the first output voltage and the polarity for amplifying the first output voltage and for changing over between amplified first output voltage and an inverted voltage of the amplified first output voltage to generate a second output voltage in accordance with the polarity. The circuit also includes an integrating amplifier circuit for integrating the second output voltage to generate an integrated signal and a variable resistance element connected between one of the voltage output terminals of the Hall element and ground, and connected to receive the integrated signal. The resistance thereof is changed by the integrated signal so that an offset voltage of the Hall element is reduced to zero.

REFERENCES:
patent: 4525668 (1985-06-01), Lienhard et al.
patent: 4608533 (1986-08-01), Starkie
patent: 4808918 (1989-02-01), Rozman
patent: 4853620 (1989-08-01), Halder et al.
patent: 4972141 (1990-11-01), Rozman et al.
Patent Abstracts of Japan, vol. 7, No. 113 (P-197), May 18, 1983, JP-A-58034365, Feb. 28, 1983.

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