Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
1999-10-26
2001-03-06
Han, Jessica (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C363S056070
Reexamination Certificate
active
06198263
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electrical circuits for the control of dead time in switching circuits, and more particularly to a power MOSFET designed for such control.
2. Description of Related Art
The following art defines the present state of this field:
The prior art teaches that in high efficiency switch-mode power systems and amplifiers using PMOS and NMOS transistors, if both are switched on at the same time there will be a conduction path between them which can result in degraded efficiency, degraded fidelity, and even destruction of the transistors. Therefore, a minimum, or near zero, dead time is introduced between the turn-on cycles of the two devices to ensure that no such conduction path exists. However, this may lead to inefficient operation and distortion. The prior art does not teach the direct control, through feedback, of an arbitrarily chosen dead time introduced into circuit operation to maximize performance. The present invention fulfills these needs and provides further related advantages as described in the following summary.
SUMMARY OF THE INVENTION
The present invention teaches certain benefits in construction and use which give rise to the objectives described below.
The present invention provides an electrical circuit design for the precise control of the dead time in a switch mode power system.
A primary objective of the present invention is to provide a switch mode power system circuit having advantages not taught by the prior art.
Another objective is provide such a circuit having precise dead time control.
A further objective is to enable the use of such a circuit whereby distortion is minimized and overall amplifier efficiency is enhanced.
Other features and advantages of the present invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention.
REFERENCES:
patent: 5631810 (1997-05-01), Takano
patent: 5747972 (1998-05-01), Baretich et al.
Gene Scott-Patent Law & Venture Group
Han Jessica
Integrated Power Technologies, Inc.
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