1990-11-06
1992-03-10
James, Andrew J.
357 238, 357 13, 357 20, H01L 2978
Patent
active
050953435
ABSTRACT:
A VDMOS device includes a wafer of semiconductor material having first and second opposed major surfaces. A drain region of a first conductivity type extends along the one major surface. A plurality of body regions of a second conductivity type is in the body region at the one major surface. Each body region forms with the drain region a body/drain PN junction, the intersection of which with the first major surface is in a closed path, preferably a hexagon. A plurality of spaced source regions of the one conductivity type are in each of the body regions with each source region being positioned opposite the space between two source regions in the adjacent body region. Each source region forms with the body region a source/body PN junction. A portion of each of the source/body PN junctions is adjacent to but spaced from its respective drain/body PN junction to form a channel region therebetween. An insulated gate is over the first major surface and the channel regions. The plurality of spaced channel regions in each of the body regions provides the device with improved surface operating area.
REFERENCES:
patent: 4364073 (1982-12-01), Becke et al.
patent: 4639762 (1987-01-01), Neilson
patent: 4823176 (1989-04-01), Baliga
"Safe Operating Area for 1200-V Nonlatchup Bipolar-Mode MOSFET's" by A. Nakagawa et al., published in IEEE Transactions on Electron Devices, vol. ED-34, No. 2, Feb. 1987, pp. 351-355.
"Cell Geometry Effect on IGT Latch-Up" by H. Yilmaz, published in IEEE Electron Device Letters, vol. EDL-6, No. 8, Aug. 1985, pp. 419-421.
Klodzinski Stanley J.
Neilson John M. S.
Ronan, Jr. Harold R.
Wheatley, Jr. Carl F.
Glick K. R.
Harris Corporation
James Andrew J.
Meier Stephen D.
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