Power MOS transistor with equipotential ring

Details Power MOS transistor with equipotential ring Power MOS transistor with equipotential ring

1987-12-29

1989-03-28

LaRoche, Eugene R.

357 238, 357 53, 357 86, 357 52, H01L 2978

Patent

active

048168823

ABSTRACT:
A process for manufacturing a DMOS transistor in accordance with the present invention includes the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask (18) is used to define the polycrystalline silicon gate. A layer of silicon dioxide (20) is then formed on the polycrystalline silicon gate. A second photolithographic mask (22) is formed on the wafer. The deep body region is then formed. Thereafer, portions of the gate insulation layer not covered by the polycrystalline silicon gate are removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the polycrystalline silicon gate. A conductive layer 30 l is formed on the wafer and photolithographically patterned. A passivation layer 34 is then formed on the wafer. Several types of termination are available, involving various combinations of device perimeter regions, field plates, metallized equipotential rings, and field limiting rings. Of importance, the above-described process uses only 4 photolithographic masking steps.

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Conti et al., "Surface Breakdown in Silicon Planar Diodes Equipped with Field Plate", Solid State Electronics, 1972, vol. 15, pp. 93-105.

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